component
TPS79328DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS79328DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS79328DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input to the device. |
| 2 | GND | power_in | Regulator ground. |
| 3 | EN | input | Enable pin: driving EN high turns on the regulator and driving it low puts the regulator into shutdown mode; EN can be connected to IN if not used. |
| 4 | NR/NC | unconnected | Noise reduction pin on the legacy chip (an external capacitor here filters bandgap noise) or no-connect on the new chip (not internally connected; connect to GND for improved thermal performance or leave floating). |
| 5 | OUT | power_out | Output of the regulator. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage | VOUT | 2.744 | 2.8 | 2.856 | V | 0µA < IOUT < 200mA, 3.8V < VIN < 5.5V | 5 |
| Quiescent current (legacy chip) | IGND | 170 | 220 | µA | 0µA ≤ IO ≤ 200mA (Legacy Chip) | 5 | |
| Quiescent current (new chip) | IGND | 250 | 1000 | µA | 0µA ≤ IO ≤ 200mA (New Chip) | 5 | |
| Line regulation | ΔVOUT/ΔVIN | 0.05 | 0.12 | %/V | VOUT + 1V ≤ VIN ≤ 5.5V | 5 | |
| Load regulation | ΔVOUT/ΔIOUT | 5 | mV | 0µA ≤ IOUT ≤ 200mA | 5 | ||
| Input voltage range | VIN | 2.7 | 5.5 | V | Input voltage | 4 | |
| Continuous output current | IOUT | 0 | 200 | mA | Output current | 4 | |
| Output noise voltage | Vn | 55 | µVRMS | BW = 100Hz to 100kHz, IOUT = 200mA, CNR = 0.001µF | 6 | ||
| Output noise voltage | Vn | 36 | µVRMS | BW = 100Hz to 100kHz, IOUT = 200mA, CNR = 0.0047µF | 6 | ||
| Output noise voltage | Vn | 33 | µVRMS | BW = 100Hz to 100kHz, IOUT = 200mA, CNR = 0.01µF | 6 | ||
| Output noise voltage | Vn | 32 | µVRMS | BW = 100Hz to 100kHz, IOUT = 200mA, CNR = 0.1µF | 6 | ||
| Output noise voltage (new chip) | Vn | 69 | µVRMS | BW = 100Hz to 100kHz, IOUT = 200mA (New Chip) | 6 | ||
| Start-up time (legacy chip) | tSTR | 50 | µs | RL = 14 Ω, COUT = 1µF, CNR = 0.001µF | 6 | ||
| Start-up time (new chip) | tSTR | 500 | µs | RL = 14 Ω, COUT = 1µF (New Chip) | 6 | ||
| Output current limit (legacy chip) | ICL | 285 | 600 | mA | VOUT = 0V (Legacy Chip) | 6 | |
| Output current limit (new chip) | ICL | 320 | 460 | mA | VIN = VOUT(NOM) + 1 V, VOUT = 0.9 x VOUT(NOM) (New Chip only) | 6 | |
| Short-circuit current limit (new chip) | ISC | 175 | mA | VOUT = 0V (New Chip) | 6 | ||
| Shutdown current (legacy chip) | ISHDN | 0.07 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (Legacy Chip) | 6 | |
| Shutdown current (new chip) | ISHDN | 0.01 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (New Chip) | 6 | |
| High-level enable input voltage (legacy chip) | VEN(HI) | 1.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | ||
| High-level enable input voltage (new chip) | VEN(HI) | 0.85 | V | 2.7V ≤ VIN ≤ 5.5V (New Chip) | 6 | ||
| Low-level enable input voltage (legacy chip) | VEN(LOW) | 0 | 0.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | |
| Low-level enable input voltage (new chip) | VEN(LOW) | 0 | 0.425 | V | 2.7V ≤ VIN ≤ 5.5V (New Chip) | 6 | |
| Enable pin current | IEN | -1 | 1 | µA | VEN = 0 V | 6 | |
| Power-supply rejection ratio, 100Hz, 10mA (legacy chip) | PSRR | 70 | dB | f = 100Hz, IOUT = 10mA (Legacy Chip) | 7 | ||
| Power-supply rejection ratio, 100Hz, 10mA (new chip) | PSRR | 64 | dB | f = 100Hz, IOUT = 10mA (New Chip) | 7 | ||
| Power-supply rejection ratio, 100Hz, 200mA (legacy chip) | PSRR | 68 | dB | f = 100Hz, IOUT = 200mA (Legacy Chip) | 7 | ||
| Power-supply rejection ratio, 100Hz, 200mA (new chip) | PSRR | 65 | dB | f = 100Hz, IOUT = 200mA (New Chip) | 7 | ||
| Power-supply rejection ratio, 10kHz, 200mA (legacy chip) | PSRR | 70 | dB | f = 10kHz, IOUT = 200mA (Legacy Chip) | 7 | ||
| Power-supply rejection ratio, 10kHz, 200mA (new chip) | PSRR | 49 | dB | f = 10kHz, IOUT = 200mA (New Chip) | 7 | ||
| Power-supply rejection ratio, 100kHz, 200mA (legacy chip) | PSRR | 43 | dB | f = 100kHz, IOUT = 200mA (Legacy Chip) | 7 | ||
| Power-supply rejection ratio, 100kHz, 200mA (new chip) | PSRR | 39 | dB | f = 100kHz, IOUT = 200mA (New Chip) | 7 | ||
| Dropout voltage | VDO | 120 | 200 | mV | VIN= VOUT - 0.1V, IOUT = 200mA | 7 | |
| UVLO threshold (legacy chip) | VUVLO | 2.25 | 2.65 | V | VIN rising (Legacy Chip) | 7 | |
| UVLO threshold (new chip) | VUVLO | 1.32 | 1.6 | V | VIN rising (New Chip) | 7 | |
| UVLO hysteresis (legacy chip) | VUVLO(HYST) | 100 | mV | TJ = 25°C, VCC rising (Legacy Chip) | 7 | ||
| UVLO hysteresis (new chip) | VUVLO(HYST) | 130 | mV | TJ = 25°C, VCC rising (New Chip) | 7 | ||
| Input, enable voltage (legacy chip) | VIN, VEN, VOUT | -0.3 | 6 | V | VIN, VEN, VOUT (Legacy Chip) | 4 | |
| Input, enable voltage (new chip) | VIN, VEN | -0.3 | 6.5 | V | VIN, VEN (New Chip) | 4 | |
| Output voltage (legacy chip) | VOUT | -0.3 | 6 | V | VOUT (Legacy Chip) | 4 | |
| Output voltage (new chip) | VOUT | -0.3 | V | VOUT (New Chip), max VIN + 0.3 V (or 6.5 V, whichever is smaller) | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | Operating junction | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | Storage | 4 | |
| Enable voltage | VEN | 0 | 5.5 | V | Enable voltage | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | Operating junction temperature | 4 | |
| Input capacitor (legacy chip) | CIN | 0.1 | 1 | µF | Input capacitor (Legacy Chip) | 4 | |
| Input capacitor (new chip) | CIN | 1 | µF | Input capacitor (New Chip) | 4 | ||
| Output capacitor | COUT | 2.2 | 10 | µF | Output capacitor; minimum 4.7µF if CFF not used or VOUT < 1.8V; minimum effective 0.47µF (new chip only) | 4 | |
| Noise reduction capacitor | CNR | 0 | 10 | nF | Noise reduction capacitor (Legacy Chip only) | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 182.3 | °C/W | DBV (SOT23-5), 5 pins, New Chip | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 114.8 | °C/W | DBV (SOT23-5), 5 pins, New Chip | 5 | ||
| Junction-to-board thermal resistance | RθJB | 79.1 | °C/W | DBV (SOT23-5), 5 pins, New Chip | 5 | ||
| Junction-to-top characterization parameter | ψJT | 56.8 | °C/W | DBV (SOT23-5), 5 pins, New Chip | 5 | ||
| Junction-to-board characterization parameter | ψJB | 78.8 | °C/W | DBV (SOT23-5), 5 pins, New Chip | 5 |
CAD (KiCad official)
- Symbol:
TPS79328DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps79328dbvr-etched.step/tps79328dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps79328dbvr.step/tps79328dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
ec20aa42e23e316a, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).