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TPS793285DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS793285DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input to the device, recommended to operate from 2.7 V to 5.5 V with a 1 µF input capacitor for the new chip.
2 GND power_in Regulator ground.
3 EN input Enable pin: driving EN high turns on the regulator and driving it low puts it into shutdown, with VEN rated 0 V to 5.5 V; EN can be connected to IN if not used.
4 NR/NC passive Legacy chip: noise reduction pin where an external capacitor CNR of 0 to 10 nF filters bandgap noise; new chip: no connect, connect to GND for improved thermal performance or leave floating.
5 OUT power_out Regulated output of the device, which requires a COUT of 2.2 µF minimum up to 10 µF, with a maximum output current of 200 mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage VOUT 2.793 2.85 2.907 V 0µA < IOUT < 200mA, 3.85V < VIN < 5.5V 5
Dropout voltage (TPS793285, legacy chip only) VDO 120 200 mV VIN= VOUT - 0.1V, IOUT = 200mA 7
Quiescent current (legacy chip) IGND 170 220 µA 0µA ≤ IO ≤ 200mA (Legacy Chip) 5
Output current limit (legacy chip) ICL 285 600 mA VOUT = 0V(Legacy Chip) 6
UVLO threshold (legacy chip) VUVLO 2.25 2.65 V VIN rising (Legacy Chip) 7
Enable pin current IEN -1 1 µA VEN = 0 V 6
Low-level enable input voltage VEN(LOW) 0 0.7 V 2.7V ≤ VIN ≤ 5.5V 6
High-level enable input voltage VEN(HI) 1.7 V 2.7V ≤ VIN ≤ 5.5V 6
Shutdown current (legacy chip) ISHDN 0.07 1 µA VEN = 0V, 2.7V < VIN < 5.5V(Legacy Chip) 6
Line regulation ΔVOUT/ΔVIN 0.05 0.12 %/V VOUT + 1V ≤ VIN ≤ 5.5V 5
Load regulation ΔVOUT/ΔIOUT 5 mV 0µA ≤ IOUT ≤ 200mA 5
UVLO hysteresis (legacy chip) VUVLO(HYST) 100 mV TJ = 25°C, VCC rising (Legacy Chip) 7
Input voltage range VIN 2.7 5.5 V 4
Enable voltage VEN 0 5.5 V 4
Output current IOUT 0 200 mA 4
Operating junction temperature TJ -40 125 °C 4
Input capacitor (legacy chip) CIN 0.1 1 µF Input capacitor (Legacy Chip) 4
Output capacitor COUT 2.2 10 µF 4
Noise reduction capacitor (legacy chip) CNR 0 10 nF Legacy Chip only 4
Input voltage absolute maximum (legacy chip) VIN, VEN, VOUT -0.3 6 V (Legacy Chip) 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance RθJA 182.3 °C/W DBV (SOT23-5), new chip 5
Junction-to-case (top) thermal resistance RθJC(top) 114.8 °C/W DBV (SOT23-5), new chip 5
Junction-to-board thermal resistance RθJB 79.1 °C/W DBV (SOT23-5), new chip 5
Junction-to-top characterization parameter ψJT 56.8 °C/W DBV (SOT23-5), new chip 5
Junction-to-board characterization parameter ψJB 78.8 °C/W DBV (SOT23-5), new chip 5

CAD (KiCad official)

  • Symbol: TPS793285DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps793285dbvr-etched.step / tps793285dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps793285dbvr.step / tps793285dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 ec20aa42e23e316a, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF