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TPS79301DBVT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS79301DBVT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-6
TPS79301DBVT from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input to the device; the input voltage range is 2.7 V to 5.5 V. |
| 2 | GND | power_in | Regulator ground. |
| 3 | EN | input | Enable pin; driving EN high turns on the regulator and driving it low puts the regulator into shutdown mode, and EN can be connected to IN if not used. The enable voltage range is 0 V to 5.5 V. |
| 4 | NR/NC | passive | On the legacy chip only, an external noise-reduction capacitor (CNR of 0 to 10 nF) connected here filters bandgap noise; on the new chip it is not internally connected and may be tied to GND or left floating. |
| 5 | FB | input | Feedback input for the adjustable device; fixed-voltage DBV versions do not have this pin. |
| 6 | OUT | power_out | Output of the regulator, requiring a COUT of at least 2.2 µF, or at least 4.7 µF if CFF is not used or VOUT(nom) is below 1.8 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | 5.5 | V | 4 | ||
| Output current | IOUT | 0 | 200 | mA | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Enable voltage | VEN | 0 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 5 | V | Printed as VFB minimum, nominal VFB | 4 | ||
| Input capacitor (legacy chip) | CIN | 0.1 | 1 | µF | Legacy chip | 4 | |
| Input capacitor (new chip) | CIN | 1 | µF | New chip; column position not clear in text | 4 | ||
| Output capacitor | COUT | 2.2 | 10 | µF | Min 4.7 µF if CFF not used or VOUT < 1.8 V; min effective 0.47 µF (new chip) | 4 | |
| Noise reduction capacitor | CNR | 0 | 10 | nF | Legacy chip only | 4 | |
| Feed-forward capacitor (legacy chip) | CFF | 15 | pF | Legacy chip | 4 | ||
| Feed-forward capacitor (new chip) | CFF | 0 | 10 | 100 | nF | New chip; optional, not required for stability | 4 |
| Lower feedback resistor | R2 | 30.1 | kΩ | Legacy chip | 4 | ||
| Input voltage (absolute maximum) VIN, VEN, VOUT | VIN, VEN, VOUT | -0.3 | 6 | V | Legacy chip | 4 | |
| Input voltage (absolute maximum) VIN, VEN | VIN, VEN | -0.3 | 6.5 | V | New chip | 4 | |
| Output voltage (absolute maximum) | VOUT | -0.3 | V | New chip; max printed as VIN + 0.3 V or 6.5 V, whichever is smaller | 4 | ||
| Operating junction temperature (absolute maximum) | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Output voltage range | VOUT | 5.5 | V | TPS79301; printed as VFB to 5.5, VDROPOUT | 5 | ||
| Input voltage range | VIN | 2.7 | 5.5 | V | 5 | ||
| Continuous output current | IOUT | 0 | 200 | mA | 5 | ||
| Quiescent current (GND current) | IGND | 170 | 220 | µA | 0µA ≤ IO ≤ 200mA (Legacy Chip) | 5 | |
| Quiescent current (GND current) | IGND | 250 | 1000 | µA | 0µA ≤ IO ≤ 200mA (New Chip) | 5 | |
| Load regulation | ΔVOUT/ΔIOUT | 5 | mV | 0µA ≤ IOUT ≤ 200mA; column position not clear in text | 5 | ||
| Line regulation | ΔVOUT/ΔVIN | 0.05 | 0.12 | %/V | VOUT + 1V ≤ VIN ≤ 5.5V | 5 | |
| Output current limit | ICL | 285 | 600 | mA | VOUT = 0V (Legacy Chip) | 6 | |
| Output current limit | ICL | 320 | 460 | mA | VIN = VOUT(NOM) + 1 V, VOUT = 0.9 x VOUT(NOM) (New Chip only) | 6 | |
| Short-circuit current limit | ISC | 175 | mA | VOUT = 0V (New Chip); column position not clear in text | 6 | ||
| Shutdown current | ISHDN | 0.07 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (Legacy Chip) | 6 | |
| Shutdown current | ISHDN | 0.01 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (New Chip) | 6 | |
| High-level enable input voltage | VEN(HI) | 1.7 | V | 2.7V ≤ VIN ≤ 5.5V; printed as 1.7 to VIN | 6 | ||
| High-level enable input voltage | VEN(HI) | 0.85 | V | 2.7V ≤ VIN ≤ 5.5V (New Chip); printed as 0.85 VIN | 6 | ||
| Low-level enable input voltage | VEN(LOW) | 0 | 0.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | |
| Low-level enable input voltage | VEN(LOW) | 0 | 0.425 | V | 2.7V ≤ VIN ≤ 5.5V (New Chip) | 6 | |
| Enable pin current | IEN | -1 | 1 | µA | VEN = 0 V | 6 | |
| Feedback pin current (TPS79301) | IFB | 1 | µA | VFB = 1.8V (Legacy Chip) | 6 | ||
| Feedback pin current (TPS79301) | IFB | 0.05 | µA | VFB = 1.8V (New Chip) | 6 | ||
| Internal reference (TPS79301) | VREF | 1.201 | 1.225 | 1.25 | V | 6 | |
| UVLO threshold | VUVLO | 2.25 | 2.65 | V | VIN rising (Legacy Chip) | 7 | |
| UVLO threshold | VUVLO | 1.32 | 1.6 | V | VIN rising (New Chip) | 7 | |
| UVLO hysteresis | VUVLO(HYST) | 100 | mV | TJ = 25°C, VCC rising (Legacy Chip) | 7 | ||
| UVLO hysteresis | VUVLO(HYST) | 130 | mV | TJ = 25°C, VCC rising (New Chip) | 7 | ||
| Junction-to-ambient thermal resistance | RθJA | 225.1 | °C/W | DBV (SOT23-6), legacy chip | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 171.7 | °C/W | DBV (SOT23-6), new chip | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 78.4 | °C/W | DBV (SOT23-6), legacy chip | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 110.8 | °C/W | DBV (SOT23-6), new chip | 5 | ||
| Junction-to-board thermal resistance | RθJB | 54.7 | °C/W | DBV (SOT23-6), legacy chip | 5 | ||
| Junction-to-board thermal resistance | RθJB | 85.4 | °C/W | DBV (SOT23-6), new chip | 5 | ||
| Junction-to-top characterization parameter | ψJT | 3.3 | °C/W | DBV (SOT23-6), legacy chip | 5 | ||
| Junction-to-top characterization parameter | ψJT | 54.4 | °C/W | DBV (SOT23-6), new chip | 5 | ||
| Junction-to-board characterization parameter | ψJB | 53.8 | °C/W | DBV (SOT23-6), legacy chip | 5 | ||
| Junction-to-board characterization parameter | ψJB | 85.2 | °C/W | DBV (SOT23-6), new chip | 5 |
CAD (KiCad official)
- Symbol:
TPS79301DBVT - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tps79301dbvt-etched.step/tps79301dbvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps79301dbvt.step/tps79301dbvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
ec20aa42e23e316a, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).