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TPS78518QKVURQ1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TO-252-4. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS78518QKVURQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TO-252-4

TPS78518QKVURQ1 from Texas Instruments, in a TO-252-4. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable pin: driving it to logic high enables the device and driving it to logic low disables it, and it must not be left floating (if unused, connect EN to IN).
2 IN input Input pin: place the nominal recommended ceramic capacitor or larger from IN to GND as close to the device as possible, per the Recommended Operating Conditions table.
3 GND power_in Ground pin that must be connected to ground on the board; the thermal pad is electrically connected to this pin.
4 OUT output Output pin requiring a minimum of 0.47 µF effective capacitance to ground for stability, with a 1 µF or larger ceramic capacitor recommended for best transient response.
5 NC unconnected No-connect pin that is not internally connected; connect to ground for best thermal performance or leave floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TO-252-4
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN 1.7 6 V 6
Output voltage (fixed option) VOUT 0.65 5 V Fixed output 6
Output accuracy VOUT -0.5 0.5 % 1 mA ≤ IOUT ≤ 1 A, VOUT(nom)+0.75 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; TJ = 25°C 7
Output accuracy VOUT -1 1 % 1 mA ≤ IOUT ≤ 1 A, VOUT(nom)+0.75 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 85°C 7
Output accuracy VOUT -1.7 1.7 % 1 mA ≤ IOUT ≤ 1 A, VOUT(nom)+0.75 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 150°C 7
Load regulation VOUT -7.5 7.5 mV 0.1 mA ≤ IOUT ≤ 1 A; –40°C ≤ TJ ≤ 85°C 7
Load regulation (VOUT ≤ 3.3 V) VOUT -7.5 15 mV 0.1 mA ≤ IOUT ≤ 1 A, –40°C ≤ TJ ≤ 150°C, VOUT ≤ 3.3 V 7
UVLO threshold, VIN rising VUVLO 1.28 1.42 1.62 V VIN rising 8
UVLO threshold, VIN falling VUVLO 1.17 1.29 1.42 V VIN falling 8
Ground current IGND 15 25 33 µA IOUT = 0 mA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; TJ = 25°C 7
Ground current IGND 35 µA IOUT = 0 mA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 85°C 7
Ground current IGND 40 µA IOUT = 0 mA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 150°C 7
Ground current IGND 33 44 µA IOUT = 500 µA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; TJ = 25°C 7
Ground current IGND 47 µA IOUT = 500 µA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 85°C 7
Ground current IGND 50 µA IOUT = 500 µA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 150°C 7
Ground current IGND 45 µA IOUT = 100 µA, VOUT(nom)+0.5 V or 2.0 V (whichever greater) ≤ VIN ≤ 6.0 V; –40°C ≤ TJ ≤ 85°C 7
Shutdown current ISHDN 0.01 0.05 µA VEN ≤ 0.3 V; TJ = 25°C 7
Shutdown current ISHDN 0.25 µA VEN ≤ 0.3 V; –40°C ≤ TJ ≤ 85°C 7
Shutdown current ISHDN 3 µA VEN ≤ 0.3 V; –40°C ≤ TJ ≤ 150°C 7
Output current limit ICL 1.04 1.65 A VIN = VOUT(nom)+1.25 V or 2.0 V (whichever greater), VOUT = 0.9 x VOUT(nom) 7
Dropout voltage (KVU package) VDO 540 mV IOUT = 1 A, VOUT = 0.95 x VOUT(nom); 1.8 V ≤ VOUT < 2.5 V 8
Dropout voltage (KVU package) VDO 500 mV IOUT = 850 mA, VOUT = 0.95 x VOUT(nom); VOUT = 1.8 V 8
Start-up time tSTR 280 550 785 µs From EN low-to-high transition to VOUT = VOUT(nom) x 92% 8
EN pin logic high voltage VEN(HI) 0.9 V 8
EN pin logic low voltage VEN(LOW) 0.3 V 8
Enable pin current IEN 10 nA VIN = VEN = 6.0 V 8
Enable voltage VEN 0 6 V 6
Output current IOUT 0 1 A 6
Input capacitor CIN 0.1 1 µF 6
Output capacitor COUT 1 200 µF 6
Feed-forward capacitor CFF 0 10 100 nF 6
Output capacitor ESR COUT,ESR 0.001 1 Ω 6
Enable toggle frequency FEN 10 kHz 6
Junction temperature (operating) TJ -40 150 °C 6
Supply voltage VIN -0.3 6.5 V Absolute maximum, with respect to GND 5
Enable voltage VEN -0.3 6.5 V Absolute maximum 5
Output voltage VOUT -0.3 V Maximum is VIN + 0.3 V or 6.5 V, whichever is smaller 5
Operating junction temperature TJ -40 150 °C Absolute maximum 5
Storage temperature Tstg -65 150 °C Absolute maximum 5
Thermal shutdown temperature TSD(shutdown) 170 °C Shutdown, temperature increasing 8
Thermal shutdown reset temperature TSD(reset) 155 °C Reset, temperature decreasing 8
Short-circuit current limit ISC 550 mA VOUT = 0 V 7
Junction-to-ambient thermal resistance (KVU) RθJA 31.6 °C/W KVU (TO-252), 5-pin 6
Junction-to-case (top) thermal resistance (KVU) RθJC(top) 40.4 °C/W KVU (TO-252), 5-pin 6
Junction-to-board thermal resistance (KVU) RθJB 10.4 °C/W KVU (TO-252), 5-pin 6
Junction-to-top characterization parameter (KVU) ψJT 4.6 °C/W KVU (TO-252), 5-pin 6
Junction-to-board characterization parameter (KVU) ψJB 10.3 °C/W KVU (TO-252), 5-pin 6
Junction-to-case (bottom) thermal resistance (KVU) RθJC(bot) 3.3 °C/W KVU (TO-252), 5-pin 6

CAD (KiCad official)

  • Symbol: TPS78518QKVURQ1
  • Footprint: Package_TO_SOT_SMD:TO-252-4
  • 3D model: TO-252-4 (KiCad packages3D, STEP)
  • 3D model files: tps78518qkvurq1-etched.step / tps78518qkvurq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps78518qkvurq1.step / tps78518qkvurq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 8d1b76473f2a1cce, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF