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TPS78411QWDRBRQ1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS78411QWDRBRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SON-8-EP(3x3)

TPS78411QWDRBRQ1 from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output pin; a 0.47-µF or greater effective capacitance is required from OUT to ground for stability, and a 1-µF or larger ceramic capacitor is recommended for best transient response.
2 NC unconnected No-connect pin that is not internally connected; connect to ground for best thermal performance or leave floating.
3 NC unconnected No-connect pin that is not internally connected; connect to ground for best thermal performance or leave floating.
4 NC unconnected No-connect pin that is not internally connected; connect to ground for best thermal performance or leave floating.
5 GND power_in Ground pin that must be connected to ground on the board; the thermal pad is electrically connected to this pin.
6 NC unconnected No-connect pin that is not internally connected; connect to ground for best thermal performance or leave floating.
7 EN input Enable pin: driving it to logic high enables the device and driving it to logic low disables it; do not float this pin, and connect it to IN if not used.
8 IN power_in Input supply pin with an absolute maximum of VIN -0.3 V to 6.5 V; use the recommended ceramic capacitor from IN to ground, placed as close to the device as possible, for best transient response.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SON-8-EP(3x3)
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VIN -0.3 6.5 V 5
Enable voltage (absolute maximum) VEN -0.3 6.5 V 5
Output voltage (absolute maximum) VOUT -0.3 V Printed maximum is VIN + 0.3 V or 6.5 V, whichever is smaller (footnote 2) 5
Operating junction temperature (absolute maximum) TJ -40 150 °C 5
Storage temperature (absolute maximum) Tstg -65 150 °C 5
Input voltage (recommended) VIN 1.65 6 V 6
Output voltage, fixed output (recommended) VOUT 0.65 5 V Fixed output 6
Input capacitor (recommended) CIN 0.1 1 µF 6
Output capacitor (recommended) COUT 1 200 µF Footnote (1): minimum effective capacitance is 0.47 µF 6
Output current (recommended) IOUT 0 300 mA 6
Output capacitor ESR (recommended) COUT,ESR 0.001 1 Ω 6
Enable voltage (recommended) VEN 0 6 V 6
Enable toggle frequency (recommended) FEN 10 kHz 6
Junction temperature (recommended) TJ -40 150 °C 6
Input voltage VIN 1.65 6 V 7
Output voltage, fixed output VOUT 0.65 5 V Fixed output 7
Output accuracy VOUT -0.5 0.5 % TJ = 25°C; 1 mA ≤ IOUT ≤ 300 mA; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Output accuracy VOUT -1 1 % –40°C ≤ TJ ≤ 85°C; 1 mA ≤ IOUT ≤ 300 mA; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Output accuracy VOUT -1.7 1.7 % –40°C ≤ TJ ≤ 150°C; 1 mA ≤ IOUT ≤ 300 mA; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Load regulation VOUT -5 5 mV 0.1 mA ≤ IOUT ≤ 300 mA; –40°C ≤ TJ ≤ 85°C 7
Load regulation VOUT -5 10 mV 0.1 mA ≤ IOUT ≤ 300 mA; –40°C ≤ TJ ≤ 150°C 7
Load transient response overshoot, undershoot ΔVOUT -2 %VOUT IOUT = 90 mA to 210 mA; tR = tF = 1 µs, COUT = 10 µF 7
Load transient response overshoot, undershoot ΔVOUT 10 %VOUT IOUT = 210 mA to 90 mA; tR = tF = 1 µs, COUT = 10 µF 7
Load transient response overshoot, undershoot ΔVOUT -10 %VOUT IOUT = 0 mA to 300 mA; tR = tF = 1 µs, COUT = 10 µF 7
Ground current IGND 15 25 30 µA IOUT = 0 mA; TJ = 25°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Ground current IGND 33 µA IOUT = 0 mA; –40°C ≤ TJ ≤ 85°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Ground current IGND 40 µA IOUT = 0 mA; –40°C ≤ TJ ≤ 150°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Ground current IGND 33 43 µA IOUT = 500 µA; TJ = 25°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Ground current IGND 45 µA IOUT = 500 µA; –40°C ≤ TJ ≤ 85°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Ground current IGND 48 µA IOUT = 500 µA; –40°C ≤ TJ ≤ 150°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Shutdown current ISHDN 0.01 0.05 µA VEN ≤ 0.3 V; TJ = 25°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Shutdown current ISHDN 0.25 µA VEN ≤ 0.3 V; –40°C ≤ TJ ≤ 85°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Shutdown current ISHDN 3 µA VEN ≤ 0.3 V; –40°C ≤ TJ ≤ 150°C; VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN ≤ 6.0 V 7
Output current limit ICL 320 420 mA VIN = VOUT(nom) + 1 V, VOUT = 0.9 x VOUT(nom) 7
Dropout voltage VDO 775 mV IOUT = 300 mA, VOUT = 0.95 x VOUT(nom); 0.8 V ≤ VOUT < 1.2 V 7
UVLO threshold, VIN rising VUVLO 1.32 1.42 1.6 V VIN rising 7
UVLO threshold, VIN falling VUVLO 1.17 1.29 1.42 V VIN falling 7
Start-up time tSTR 280 500 780 µs From EN low-to-high transition to VOUT = VOUT(nom) x 95% 7
EN pin logic high voltage VEN(HI) 0.85 V 8
EN pin logic low voltage VEN(LOW) 0.425 V 8
Enable pin current IEN 10 nA VIN = VEN = 6.0 V 8
Junction-to-ambient thermal resistance (DRB VSON) RθJA 61.8 °C/W 6
Junction-to-case (top) thermal resistance (DRB VSON) RθJC(top) 74.1 °C/W 6
Junction-to-board thermal resistance (DRB VSON) RθJB 34.3 °C/W 6
Junction-to-top characterization parameter (DRB VSON) ψJT 6.2 °C/W 6
Junction-to-board characterization parameter (DRB VSON) ψJB 34.1 °C/W 6
Junction-to-case (bottom) thermal resistance (DRB VSON) RθJC(bot) 18.1 °C/W 6

CAD (KiCad official)

  • Symbol: TPS78411QWDRBRQ1
  • Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps78411qwdrbrq1-etched.step / tps78411qwdrbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps78411qwdrbrq1.step / tps78411qwdrbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 0c6f0cf1abccc5c1, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF