component
TPS77301DGKR
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS77301DGKR
Texas Instruments · Linear Voltage Regulators (LDO) · VSSOP-8
TPS77301DGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB/SENSE | input | Feedback input for the adjustable device, which must connect to an external feedback resistor divider, and sense input for fixed options, which must connect to the regulator output as short as possible. |
| 2 | RESET | output | Open-drain, active-low reset output that goes high-impedance after a 220-ms delay once OUT reaches 95% of its regulated voltage and requires a pullup resistor. |
| 3 | EN | input | Enable input where a logic low enables the regulator and a logic high shuts it down. |
| 4 | GND | power_in | Regulator ground (signal ground for the output capacitor return). |
| 5 | IN | power_in | Input voltage supply to the PMOS pass element; the datasheet pages provided do not state an input voltage limit for this pin. |
| 6 | IN | power_in | Input voltage supply to the PMOS pass element; the datasheet pages provided do not state an input voltage limit for this pin. |
| 7 | OUT | power_out | Regulated output voltage that requires an output capacitor to GND of at least 1 µF with ESR within Figures 19 and 21, or at least 10 µF for low-ESR capacitors meeting Figures 18 and 20. |
| 8 | OUT | power_out | Regulated output voltage that requires an output capacitor to GND of at least 1 µF with ESR within Figures 19 and 21, or at least 10 µF for low-ESR capacitors meeting Figures 18 and 20. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Adjustable output voltage accuracy (multiplier of VO) | VO | 0.98 | 1.02 | VO (multiplier) | 1.5 V ≤ VO ≤ 5.5 V | 7 | |
| Output voltage line regulation (ΔVO/VO) | 0.05 | %/V | VO + 1 V < VI ≤ 10 V | 7 | |||
| Quiescent current (GND current) | 125 | µA | 7 | ||||
| Standby current | 3 | µA | EN = VI | 8 | |||
| FB input current | 1 | µA | FB = 1.5 V | 8 | |||
| High level enable input voltage | 2 | V | 8 | ||||
| Enable input current | -1 | 1 | µA | 8 | |||
| RESET trip threshold voltage | 92 | 98 | %VO | VO decreasing | 8 | ||
| Minimum input voltage for valid RESET | 1.1 | V | I(RESET) = 300 µA | 8 | |||
| RESET output low voltage | 0.15 | 0.4 | V | VI = 2.7 V, I(RESET) = 1 mA | 8 | ||
| RESET leakage current | 1 | µA | V(RESET) = 5 V | 8 | |||
| RESET hysteresis voltage | 0.5 | %VO | Measured at VO | 8 | |||
| Load regulation | 1 | mV | TJ = 25°C | 7 | |||
| Output voltage line regulation (ΔVO/VO) | 0.005 | %/V | VO + 1 V < VI ≤ 10 V, TJ = 25°C | 7 | |||
| Quiescent current (GND current) | 92 | µA | TJ = 25°C | 7 | |||
| Peak output current | 400 | mA | 2 ms pulse width, 50% duty cycle | 7 | |||
| Thermal shutdown junction temperature | 144 | °C | 7 | ||||
| Standby current | 1 | µA | EN = VI, TJ = 25°C | 7 | |||
| RESET time-out delay | 220 | ms | 8 | ||||
| Input voltage | VI | 2.7 | 10 | V | 6 | ||
| Output voltage range | VO | 1.5 | 5.5 | V | 6 | ||
| Output current | IO | 0 | 250 | mA | see Note 1 | 6 | |
| Operating virtual junction temperature | TJ | -40 | 125 | °C | see Note 1 | 6 | |
| Input voltage range | VI | -0.3 | 13.5 | V | 6 | ||
| Voltage range at EN | -0.3 | 16.5 | V | 6 | |||
| Maximum RESET voltage (TPS773xx) | 16.5 | V | 6 | ||||
| Output voltage (OUT, FB) | VO | 5.5 | V | 6 | |||
| Operating virtual junction temperature range | TJ | -40 | 125 | °C | 6 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 6 | ||
| ESD rating, HBM | 2 | kV | HBM | 6 | |||
| Junction-to-ambient thermal resistance (DGK) | θJA | 266.2 | °C/W | 0 CFM air flow | 6 | ||
| Junction-to-case thermal resistance (DGK) | θJC | 3.84 | °C/W | 0 CFM air flow | 6 |
CAD (KiCad official)
- Symbol:
TPS77301DGKR - Footprint:
Package_SO:VSSOP-8_3x3mm_P0.65mm - 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
tps77301dgkr-etched.step/tps77301dgkr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps77301dgkr.step/tps77301dgkr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
e831bc9de40e35b4, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).