# TPS77001DBVT

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS77001DBVT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input pin: operates from 2.5 V to 16 V (new chip, absolute maximum 18 V); place the recommended input capacitor as close as possible to the IN and GND pins. |
| 2 | GND | power_in | Ground pin; all voltages are referenced to GND. |
| 3 | EN | input | Active-low enable: driving EN low enables the device and driving it high disables it, with the EN high and low thresholds given in the Electrical Characteristics table (new chip EN voltage 0 V to 16 V recommended, absolute maximum 18 V); the new chip has an internal pull-up, so leaving EN floating disables the LDO. |
| 4 | FB/NC | input | On the adjustable version (TPS76901-Q1) this is the feedback pin that sets the output voltage through external resistors and must not be left floating (new chip FB voltage absolute maximum 3 V, reference 1.2 V); on fixed versions it is no connect and should not be connected on the new chip. |
| 5 | OUT | output | Output pin: regulates from 1.2 V to 5.5 V at up to 100 mA, and the output capacitor must be placed as close as possible to the OUT and GND pins (new chip COUT 2.2 µF minimum, ESR 0 Ω to 3 Ω recommended). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN (old chip) | VIN | 2.7 |  | 10 | V |  | 4 |
| Input voltage VIN (new chip) | VIN | 2.5 |  | 16 | V |  | 4 |
| Output voltage VOUT (old chip, adjustable) | VOUT | 1.25 |  | 5.5 | V |  | 4 |
| Output voltage VOUT (new chip, adjustable) | VOUT | 1.2 |  | 5.5 | V |  | 4 |
| Enable voltage VEN (old chip); printed max is VIN | VEN | 0 |  |  | V |  | 4 |
| Enable voltage VEN (new chip) | VEN | 0 |  | 16 | V |  | 4 |
| Output current IOUT | IOUT | 0 |  | 100 | mA |  | 4 |
| Output capacitor COUT (new chip) | COUT | 2.2 |  | 200 | µF |  | 4 |
| Output capacitor ESR range (old chip) | ESR | 0.2 |  | 10 | Ω |  | 4 |
| Output capacitor ESR range (new chip) | ESR | 0 |  | 3 | Ω |  | 4 |
| Operating junction temperature TJ | TJ | -40 |  | 125 | °C |  | 4 |
| Continuous input voltage VIN (old chip) | VIN | -0.3 |  | 13.5 | V |  | 3 |
| Continuous input voltage VIN (new chip) | VIN | -0.3 |  | 18 | V |  | 3 |
| Output voltage VOUT (old chip) | VOUT | -0.3 |  | 7 | V |  | 3 |
| Output voltage VOUT (new chip); printed max is VIN + 0.3 or 7 V, whichever is lower | VOUT | -0.3 |  |  | V |  | 3 |
| FB pin voltage (old chip) | VFB | -0.3 |  | 7 | V |  | 3 |
| FB pin voltage (new chip) | VFB | -0.3 |  | 3 | V |  | 3 |
| EN pin voltage (old chip); printed max is VIN + 0.3 | VEN | -0.3 |  |  | V |  | 3 |
| EN pin voltage (new chip) | VEN | -0.3 |  | 18 | V |  | 3 |
| Operating junction temperature TJ (old chip) | TJ | -40 |  | 150 | °C |  | 3 |
| Operating junction temperature TJ (new chip) | TJ | -55 |  | 150 | °C |  | 3 |
| Storage temperature Tstg | Tstg | -65 |  | 150 | °C |  | 3 |
| Output voltage accuracy (old chip, adjustable), full range | VOUT | 0.97 |  | 1.03 | × VOUT | 1.2V ≤ VOUT ≤ 5.5V，10µA ≤ IOUT ≤ 100mA | 5 |
| Output voltage line regulation (old chip) | ΔVOUT/VOUT | 0.04 | 0.07 | 0.1 | %/V | VOUT(NOM) +1.0V ≤ VIN ≤ 10V，IOUT = 100mA，TJ = 25℃ | 5 |
| Quiescent current IQ (new chip, adjustable) | IQ |  | 50 | 80 | µA | EN = 0V，IOUT = 0mA（可调节） | 5 |
| Standby current ISTANDBY (old chip) | ISTANDBY |  | 1 | 2 | µA | EN = VIN，2.7V < VIN < 10V | 6 |
| Standby current ISTANDBY (new chip) | ISTANDBY |  | 0.9 | 2.75 | µA | EN = VIN，2.5V < VIN < 16V | 6 |
| FB pin current IFB (old chip) | IFB | -1 |  | 1 | µA | VFB = 1.224V | 6 |
| FB pin current IFB (new chip) | IFB | -0.1 |  | 0.1 | µA | VFB = 1.2V | 6 |
| EN high-level input voltage (old chip) |  | 1.7 |  |  | V | 2.7V ≤ VIN ≤ 10V | 6 |
| EN low-level input voltage (old chip) |  |  |  | 0.9 | V |  | 6 |
| EN high-level input voltage (new chip) |  | 1.6 |  |  | V | 2.5V ≤ VIN ≤ 16V | 6 |
| EN low-level input voltage (new chip) |  |  |  | 0.415 | V |  | 6 |
| EN input current IEN (old chip) | IEN | -1 | 0 | 1 | µA | EN = 0V | 6 |
| EN input current IEN (old chip) | IEN | -1 |  | 1 | µA | EN = VIN | 6 |
| EN input current IEN (new chip) | IEN | -0.75 | -0.4 | 0.02 | µA | EN = 0V | 6 |
| EN input current IEN (new chip) | IEN | -0.01 |  | 0.01 | µA | EN = 6V | 6 |
| Output current limit ICL (old chip) | ICL | 350 |  | 750 | mA | VOUT = 0V | 6 |
| Output current limit ICL (new chip) | ICL | 370 |  | 450 | mA |  | 6 |
| UVLO rising threshold (new chip; table labelled TPS769) | VUVLO+ | 2.2 |  | 2.4 | V | VIN 上升，–40℃ ≤ TJ ≤ 125℃ | 7 |
| UVLO falling threshold (new chip; table labelled TPS769) | VUVLO- | 1.9 |  | 2.07 | V | VIN 下降，–40℃ ≤ TJ ≤ 125℃ | 7 |
| FB voltage VFB (old chip) | VFB |  | 1.224 |  | V |  | 4 |
| FB voltage VFB (new chip) | VFB |  | 1.2 |  | V |  | 4 |
| Input capacitor CIN | CIN |  | 1 |  | µF |  | 4 |
| Output capacitor COUT (old chip) | COUT |  | 4.7 |  | µF |  | 4 |
| Junction-to-ambient thermal resistance (new chip, DBV 5-pin) | RθJA |  | 178.6 |  | °C/W |  | 4 |
| Junction-to-case (top) thermal resistance (new chip) | RθJC(top) |  | 77.9 |  | °C/W |  | 4 |
| Junction-to-board thermal resistance (new chip) | RθJB |  | 47.2 |  | °C/W |  | 4 |
| Junction-to-top characterization parameter (new chip) | ψJT |  | 15.9 |  | °C/W |  | 4 |
| Junction-to-board characterization parameter (new chip) | ψJB |  | 46.9 |  | °C/W |  | 4 |
| Junction-to-case thermal resistance (old chip) | RθJC |  | 65.8 |  | °C/W |  | 5 |
| Junction-to-ambient thermal resistance (old chip) | RθJA |  | 259 |  | °C/W | 低 K (1s) board | 5 |
| Junction-to-ambient thermal resistance (old chip) | RθJA |  | 180 |  | °C/W | 高 K (2s2p) board | 5 |

## CAD (KiCad official)

- Symbol: `TPS77001DBVT`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps77001dbvt-etched.step` / `tps77001dbvt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps77001dbvt.step` / `tps77001dbvt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps770) (41 pp, sha256 `5d7502386c6f6cd7`, retrieved 2026-10-12, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps77001dbvt-datasheet.pdf)