component
TPS76930QDBVRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS76930QDBVRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS76930QDBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input pin: use the recommended input capacitor value from the Recommended Operating Conditions (CIN 1 µF), placed as close as possible to the IN and GND pins; input voltage is 2.5 V to 16 V for the new-chip silicon (2.7 V to 10 V for the old chip). |
| 2 | GND | power_in | Ground pin, the reference for all device voltages. |
| 3 | EN | input | Enable pin: driving it low enables the device and driving it high disables it, with the low and high threshold levels given in the Electrical Characteristics table; on the new chip it has an internal pull-up, so leaving it floating disables the LDO. |
| 4 | FB/NC | unconnected | For the fixed-output version (TPS76930), this pin is no-connect: leave it unconnected on the old chip and do not connect it on the new chip. |
| 5 | OUT | output | Output pin: use the recommended output capacitor values from the Recommended Operating Conditions (COUT 2.2 µF minimum for the new chip, 4.7 µF for the old chip), placed as close as possible to the OUT and GND pins; output is rated up to 100 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
CAD (KiCad official)
- Symbol:
TPS76930QDBVRQ1 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps76930qdbvrq1-etched.step/tps76930qdbvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps76930qdbvrq1.step/tps76930qdbvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (45 pp, sha256
50207086698c1025, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS76930QDBVRQ1
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS76930QDBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input pin: use the recommended input capacitor value from the Recommended Operating Conditions (CIN 1 µF), placed as close as possible to the IN and GND pins; input voltage is 2.5 V to 16 V for the new-chip silicon (2.7 V to 10 V for the old chip). |
| 2 | GND | power_in | Ground pin, the reference for all device voltages. |
| 3 | EN | input | Enable pin: driving it low enables the device and driving it high disables it, with the low and high threshold levels given in the Electrical Characteristics table; on the new chip it has an internal pull-up, so leaving it floating disables the LDO. |
| 4 | FB/NC | unconnected | For the fixed-output version (TPS76930), this pin is no-connect: leave it unconnected on the old chip and do not connect it on the new chip. |
| 5 | OUT | output | Output pin: use the recommended output capacitor values from the Recommended Operating Conditions (COUT 2.2 µF minimum for the new chip, 4.7 µF for the old chip), placed as close as possible to the OUT and GND pins; output is rated up to 100 mA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## CAD (KiCad official)
- Symbol: `TPS76930QDBVRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps76930qdbvrq1-etched.step` / `tps76930qdbvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps76930qdbvrq1.step` / `tps76930qdbvrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps769-q1) (45 pp, sha256 `50207086698c1025`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps76930qdbvrq1-datasheet.pdf)