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TPS76927DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS76927DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS76927DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply pin; place the recommended input capacitor of at least 1 µF as close to IN and GND as possible. |
| 2 | GND | power_in | Ground reference pin for all voltages in the device. |
| 3 | EN | input | Enable pin; driving it low enables the device and driving it high disables the device. |
| 4 | FB/NC | unconnected | On the legacy fixed-voltage version this pin is not connected; the feedback function applies only to the adjustable version. |
| 5 | OUT | power_out | Regulated output pin; place the output capacitor as close to OUT and GND as possible, with at least 2.2 µF for the new chip and 4.7 µF for the legacy chip. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage (fixed, legacy chip) | VOUT | 0.97 | 1.03 | x VOUT | 10µA ≤ IOUT ≤ 100mA, VOUT(nom) + 1V < VIN < 10V | 5 | |
| Enable high level input voltage (legacy chip) | EN | 1.7 | V | 2.7V ≤ VIN ≤ 10V | 6 | ||
| Enable low level input voltage (legacy chip) | EN | 0.9 | V | 2.7V ≤ VIN ≤ 10V | 6 | ||
| Feedback pin current (legacy chip) | IFB | -1 | 1 | µA | VFB = 1.224V | 7 | |
| Input current (EN) (legacy chip) | IEN | -1 | 0 | 1 | µA | EN = 0V | 6 |
| Input current (EN) (legacy chip) | IEN | -1 | 1 | µA | EN = VIN | 6 | |
| Standby current (legacy chip) | ISTANDBY | 1 | µA | EN = VIN, 2.7V < VIN < 10V | 7 | ||
| Standby current (legacy chip) | ISTANDBY | 2 | µA | EN = VIN, 2.7V < VIN < 10V | 7 | ||
| Quiescent current (GND current) (legacy chip) | IQ | 17 | µA | EN = 0V, 0mA < IOUT < 100mA, TJ = +25°C | 5 | ||
| Quiescent current (GND current) (legacy chip) | IQ | 28 | µA | EN = 0V, IOUT = 100mA | 5 | ||
| Output voltage line regulation (legacy chip) | ΔVOUT/VOUT | 0.04 | 0.1 | %/V | VOUT(NOM) +1.0V ≤ VIN ≤ 10V, IOUT = 100mA, TJ = 25℃ | 5 | |
| Input voltage (legacy chip) | VIN | 2.7 | 10 | V | Supply input voltage (legacy chip) | 4 | |
| Output voltage (legacy chip) | VOUT | 1.25 | 5.5 | V | Output voltage (legacy chip) | 4 | |
| Output current | IOUT | 0 | 100 | mA | Output current | 4 | |
| Output capacitor (legacy chip) | COUT | 4.7 | µF | Output capacitor (legacy chip) | 4 | ||
| ESR range (legacy chip) | ESR | 0.2 | 10 | Ω | ESR range (legacy chip) | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | Operating junction temperature | 4 | |
| Enable voltage (legacy chip) | VEN | 0 | V | Enable voltage (legacy chip), maximum VIN | 4 | ||
| Continuous input voltage (legacy chip) | VIN | -0.3 | 13.5 | V | Continuous input voltage (legacy chip) | 3 | |
| Output voltage (legacy chip) | VOUT | -0.3 | 7 | V | Output voltage (legacy chip) | 3 | |
| FB pin voltage (legacy chip) | VFB | -0.3 | 7 | V | FB pin voltage (legacy chip) | 3 | |
| EN pin voltage (legacy chip) | VEN | -0.3 | V | EN pin voltage (legacy chip), upper limit VIN + 0.3 | 3 | ||
| Operating junction temperature (legacy chip) | TJ | -40 | 150 | °C | Operating junction temperature (legacy chip) | 3 | |
| Storage temperature | Tstg | -65 | 150 | °C | Storage | 3 | |
| Junction-to-ambient thermal resistance (legacy chip, Low K) | RθJA | 259 | °C/W | Low K (1s) board | 5 | ||
| Junction-to-ambient thermal resistance (legacy chip, High K) | RθJA | 180 | °C/W | High K (2s2p) board | 5 | ||
| Junction-to-case thermal resistance (legacy chip) | RθJC | 65.8 | °C/W | Low K and High K | 5 |
CAD (KiCad official)
- Symbol:
TPS76927DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps76927dbvr-etched.step/tps76927dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps76927dbvr.step/tps76927dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (46 pp, sha256
8b45e7f7d5e0947e, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).