# TPS76850QD

**Texas Instruments** · Low Dropout Regulators(LDO) · SOIC-8

TPS76850QD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Regulator ground pin; the output capacitor must be connected between OUT and GND to stabilize the control loop. |
| 2 | EN | input | Enable input; a TTL high signal shuts down the regulator, and EN should be tied to ground if the shutdown feature is not used. |
| 3 | IN | power_in | Input voltage, specified from 2.7 V to 10 V, with VIN at least VOUT + VDO or 2.7 V, whichever is greater. |
| 4 | IN | power_in | Input voltage, specified from 2.7 V to 10 V, with VIN at least VOUT + VDO or 2.7 V, whichever is greater. |
| 5 | OUT | power_out | Regulated output voltage; the output capacitor needs a minimum of 10 µF with ESR between 60 mΩ and 1.5 Ω. |
| 6 | OUT | power_out | Regulated output voltage; the output capacitor needs a minimum of 10 µF with ESR between 60 mΩ and 1.5 Ω. |
| 7 | FB/NC | unconnected | Feedback input voltage for the adjustable device; no connect for fixed-output options such as the 5.0 V TPS76850. |
| 8 | PG | output | Open-drain power-good output that pulls low when the output drops to between 92% and 98% of its nominal regulated value and requires a pullup resistor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output current limit |  | 1.2 | 1.7 | 2 | A | VO = 0 V | 3 |
| Dropout voltage |  |  |  | 380 | mV | IO = 1 A, TJ = -40°C to +125°C (TPS76850) | 3 |
| Quiescent current (GND current) |  |  |  | 125 | µA | IO = 1 A, TJ = -40°C to +125°C | 3 |
| Standby current |  |  |  | 1 | µA | VEN = VI, TJ = +25°C, 2.7 V < VI < 10 V | 3 |
| Standby current |  |  |  | 10 | µA | VEN = VI, TJ = -40°C to +125°C, 2.7 V < VI < 10 V | 3 |
| High-level enable input voltage |  | 1.7 |  |  | V |  | 3 |
| Low-level enable input voltage |  |  |  | 0.9 | V |  | 3 |
| Trip threshold voltage |  | 92 |  | 98 | %VO | VO decreasing | 3 |
| Output low voltage |  |  | 0.15 | 0.4 | V | VI = 2.7 V, IO(PG) = 1 mA | 3 |
| Minimum input voltage for valid PG |  |  |  | 1.1 | V | IO(PG) = 300 µA | 3 |
| Leakage current (PG) |  |  |  | 1 | µA | V(PG) = 5 V | 3 |
| Enable pin current (IEN), VEN = 0 V | IEN |  | 0 | 1 | µA | VEN = 0 V | 3 |
| Enable pin current (IEN), VEN = VI | IEN |  | 1 | 1 | µA | VEN = VI | 3 |
| Load regulation |  |  |  | 3 | mV |  | 3 |
| Output voltage line regulation | ΔVO/VO |  | 0.01 |  | %/V | VO + 1 V < VI ≤ 10 V, TJ = +25°C | 3 |
| Dropout voltage |  |  | 230 |  | mV | IO = 1 A, TJ = +25°C (TPS76850) | 3 |
| Quiescent current (GND current) |  |  | 85 |  | µA | 10 µA < IO < 1 A, TJ = +25°C, EN = 0 V | 3 |
| Thermal shutdown junction temperature |  |  | 150 |  | °C |  | 3 |
| Power-supply ripple rejection |  |  | 60 |  | dB | f = 1 kHz, CO = 10 µF, TJ = +25°C | 3 |
| Power good hysteresis voltage |  |  | 0.5 |  | %VO | Measured at VO | 3 |
| Output voltage tolerance | VOUT | -2 |  | 2 | % | Over specified conditions, fixed-output version | 1 |
| Input voltage range | VI | 2.7 |  | 10 | V |  | 2 |
| Output current | IO | 0 |  | 1 | A |  | 2 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 2 |
| Output capacitance | CO | 10 |  |  | µF | Minimum recommended value | 11 |
| Output capacitor ESR | ESR | 60 |  |  | mΩ | Minimum ESR | 11 |
| Output capacitor ESR | ESR |  |  | 1.5 | Ω | Maximum ESR | 11 |
| Input voltage | VI | -0.3 |  | 13.5 | V |  | 2 |
| Voltage at EN | VEN | -0.3 |  |  | V | Maximum is VI + 0.3 V | 2 |
| Maximum PG voltage |  |  |  | 16.5 | V |  | 2 |
| Output voltage (OUT, FB) | VO |  |  | 7 | V |  | 2 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| ESD rating |  |  |  | 2 | kV | HBM | 2 |
| Junction-to-ambient thermal resistance | RθJA |  | 172 |  | °C/W | 8-pin SOIC (D), no airflow | 13 |
| Power rating, free-air |  |  | 568.18 |  | mW | D package, 0 CFM, TA < +25°C | 2 |
| Derating factor above TA = +25°C |  |  | 5.6818 |  | mW/°C | D package, 0 CFM | 2 |

## CAD (KiCad official)

- Symbol: `TPS76850QD`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tps76850qd-etched.step` / `tps76850qd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps76850qd.step` / `tps76850qd.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps76850qd.pdf) (26 pp, sha256 `5cff63017ac024f3`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps76850qd-datasheet.pdf)