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TPS76830QD

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS76830QD

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

TPS76830QD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Regulator ground; the datasheet gives no further electrical limit for this pin.
2 EN input Enable input: a TTL high shuts the regulator down, and EN must be tied to ground if the shutdown feature is not used; the high-level input threshold is 1.7 V minimum and the low-level threshold is 0.9 V maximum, with EN absolute voltage limited to -0.3 V to VI + 0.3 V.
3 IN power_in Input voltage: recommended range is 2.7 V to 10 V, with VIN at least VOUT + VDO (or 2.7 V, whichever is greater), and the absolute maximum input is 13.5 V.
4 IN power_in Input voltage (second input pin, internally tied to pin 3): recommended range is 2.7 V to 10 V, with absolute maximum input of 13.5 V.
5 OUT power_out Regulated output voltage; output current is rated 0 to 1.0 A, and the output requires at least 10 µF to GND with ESR between 60 mΩ and 1.5 Ω for stability.
6 OUT power_out Regulated output voltage (second output pin, internally tied to pin 5): output current is rated 0 to 1.0 A.
7 FB/NC unconnected Feedback input for the adjustable device (TPS76801, 1.2 V to 5.5 V output); for fixed-output options such as the TPS76830 this pin is no connect.
8 PG output Open-drain power-good output that goes low when the output falls to between 92% and 98% of its nominal value, requires an external pullup resistor, and has an absolute maximum voltage of 16.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output current limit 1.2 1.7 2 A VO = 0 V 3
Dropout voltage (IO = 1 A, TJ = +25°C) VDO 450 mV IO = 1 A, TJ = +25°C; TPS76830 row 3
Dropout voltage (IO = 1 A, TJ = –40°C to +125°C) VDO 675 mV IO = 1 A, TJ = –40°C to +125°C; TPS76830 row 3
Quiescent current (GND current) IQ 85 µA 10 µA < IO < 1 A, TJ = +25°C, EN = 0 V 3
Quiescent current (GND current), full temperature IQ 125 µA IO = 1 A, TJ = –40°C to +125°C, EN = 0 V 3
Standby current 1 µA VEN = VI, TJ = +25°C, 2.7 V < VI < 10 V 3
Standby current (full temperature) 10 µA VEN = VI, TJ = –40°C to +125°C, 2.7 V < VI < 10 V 3
High-level enable input voltage 1.7 V 3
Low-level enable input voltage 0.9 V 3
Trip threshold voltage 92 98 %VO VO decreasing 3
Minimum input voltage for valid PG 1.1 V IO(PG) = 300 µA 3
Output low voltage (PG) 0.15 0.4 V VI = 2.7 V, IO(PG) = 1 mA 3
Leakage current (PG) 1 µA V(PG) = 5 V 3
Input voltage range (recommended) VI 2.7 10 V Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater 2
Output current (recommended) IO 0 1 A 2
Operating junction temperature (recommended) TJ -40 125 °C 2
Input voltage range (absolute maximum) VI -0.3 13.5 V All voltage values with respect to network terminal ground 2
Maximum PG voltage 16.5 V 2
Output voltage (OUT, FB) VO 7 V 2
Operating junction temperature range (absolute maximum) TJ -40 125 °C 2
Storage temperature range Tstg -65 150 °C 2
ESD rating, HBM 2 kV HBM 2
Continuous total power rating, D package PD 568.18 mW TA < +25°C, 0 CFM air flow, D (SOIC-8) package 2
Derating factor above TA = +25°C, D package 5.6818 mW/°C 0 CFM air flow, D (SOIC-8) package 2
Power rating at TA = +70°C, D package PD 312.5 mW 0 CFM air flow, D (SOIC-8) package 2
Power rating at TA = +85°C, D package PD 227.27 mW 0 CFM air flow, D (SOIC-8) package 2
Junction-to-ambient thermal resistance, 8-pin SOIC (D) RθJA 172 °C/W No airflow 13
Thermal shutdown junction temperature 150 °C 3
Output voltage line regulation ΔVO/VO 0.01 %/V VO + 1 V < VI ≤ 10 V, TJ = +25°C 3
Load regulation 3 mV 3
Power-supply ripple rejection PSRR 60 dB f = 1 kHz, CO = 10 µF, TJ = +25°C 3
Power good hysteresis voltage 0.5 %VO Measured at VO 3

CAD (KiCad official)

  • Symbol: TPS76830QD
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps76830qd-etched.step / tps76830qd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps76830qd.step / tps76830qd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 742896d0a1cf7766, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF