# TPS76701QDR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

TPS76701QDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Regulator ground pin. |
| 2 | EN | input | Enable input; a TTL high signal shuts the regulator down, and EN should be tied to ground if the shutdown feature is not used. |
| 3 | IN | power_in | Input voltage; recommended input range is 2.7 V to 10 V, with an absolute maximum of 13.5 V. |
| 4 | IN | power_in | Input voltage; recommended input range is 2.7 V to 10 V, with an absolute maximum of 13.5 V. |
| 5 | OUT | power_out | Regulated output voltage; output current is 0 to 1.0 A and the output voltage range is 1.2 V to 5.5 V. |
| 6 | OUT | power_out | Regulated output voltage; output current is 0 to 1.0 A and the output voltage range is 1.2 V to 5.5 V. |
| 7 | FB/NC | input | Feedback input that senses the output voltage through an external resistor divider for the adjustable version, with a 1.1834 V typical reference; no connect for fixed-voltage options. |
| 8 | RESET | output | Open-drain RESET output that pulls low when the output drops to between 92% and 98% of nominal and requires a pullup resistor. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage tolerance | VO | -2 |  | 2 | % | 1.5 V ≤ VO ≤ 5.5 V, TJ = −40°C to 125°C | 6 |
| Input voltage range | VI | 2.7 |  | 10 | V |  | 5 |
| Output voltage range | VO | 1.2 |  | 5.5 | V |  | 5 |
| Output current | IO | 0 |  | 1 | A |  | 5 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 5 |
| Input voltage range | VI | -0.3 |  | 13.5 | V |  | 5 |
| Voltage range at EN |  | -0.3 |  |  | V | Printed as VI + 0.3 V maximum | 5 |
| Maximum RESET voltage |  |  |  | 16.5 | V |  | 5 |
| Output voltage (OUT, FB) | VO |  |  | 7 | V |  | 5 |
| Operating junction temperature range | TJ | -40 |  | 125 | °C |  | 5 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 5 |
| Output current limit |  | 1.2 | 1.7 | 2 | A | VO = 0 V | 6 |
| Quiescent current (GND current) |  |  |  | 125 | µA | EN = 0V; IO = 1 A, TJ = −40°C to 125°C | 6 |
| Standby current |  |  |  | 10 | µA | TJ = −40°C to 125°C, EN = VI, 2.7 V < VI < 10 V | 6 |
| High level enable input voltage |  | 1.7 |  |  | V |  | 6 |
| Low level enable input voltage |  |  |  | 0.9 | V |  | 6 |
| Trip threshold voltage |  | 92 |  | 98 | % | VO decreasing | 6 |
| Output low voltage |  |  | 0.15 | 0.4 | V | VI = 2.7 V, IO(RESET) = 1 mA | 6 |
| Input current (EN) |  | -1 | 0 | 1 | µA | EN = 0 V | 6 |
| Input current (EN) |  | -1 |  | 1 | µA | EN = VI | 6 |
| Quiescent current (GND current) |  |  | 85 |  | µA | EN = 0V; 10 µA < IO < 1 A, TJ = 25°C | 6 |
| Output voltage line regulation (∆VO/VO) |  |  | 0.01 |  | %/V | VO + 1 V < VI ≤ 10 V, TJ = 25°C | 6 |
| Load regulation |  |  | 3 |  | mV |  | 6 |
| Thermal shutdown junction temperature |  |  | 150 |  | °C |  | 6 |
| Standby current |  |  | 1 |  | µA | EN = VI, TJ = 25°C, 2.7 V < VI < 10 V | 6 |
| Power supply ripple rejection |  |  | 60 |  | dB | f = 1 kHz, Co = 10 µF, TJ = 25°C | 6 |
| Reset hysteresis voltage |  |  | 0.5 |  | % | Measured at VO | 6 |
| RESET time-out delay |  |  | 200 |  | ms |  | 6 |
| Internal reference voltage | Vref |  | 1.1834 |  | V | Internal reference voltage | 15 |
| Junction-to-ambient thermal resistance | RθJA |  | 106.9 |  | °C/W | D (SOIC, 8 pins) | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 52.5 |  | °C/W | D (SOIC, 8 pins) | 5 |
| Junction-to-board thermal resistance | RθJB |  | 47.7 |  | °C/W | D (SOIC, 8 pins) | 5 |
| Junction-to-top characterization parameter | ψJT |  | 9 |  | °C/W | D (SOIC, 8 pins) | 5 |
| Junction-to-board characterization parameter | ψJB |  | 47.1 |  | °C/W | D (SOIC, 8 pins) | 5 |

## CAD (KiCad official)

- Symbol: `TPS76701QDR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tps76701qdr-etched.step` / `tps76701qdr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps76701qdr.step` / `tps76701qdr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps767.pdf) (37 pp, sha256 `8fecf68765895723`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps76701qdr-datasheet.pdf)