component
TPS76338DBVT
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS76338DBVT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS76338DBVT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply pin; use a capacitor of 1µF or larger from this pin to ground, with input range 2.7V to 10V. |
| 2 | GND | power_in | Ground reference pin for the regulator. |
| 3 | EN | input | Enable pin; driving it high enables the device and driving it low disables it, and it should be tied to VIN if unused (new chip). |
| 4 | NC | unconnected | No connection on the fixed-voltage option; the FB feedback function applies only to the adjustable device. |
| 5 | OUT | power_out | Regulator output; use a capacitor of 2.2µF or larger from this pin to ground, with nominal output capacitance greater than 1µF after derating. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage | VOUT | 3.724 | 3.8 | 3.876 | V | IOUT = 1mA to 100mA, TJ = 25°C | 7 |
| Output voltage | VOUT | 3.705 | 3.8 | 3.895 | V | IOUT = 1mA to 100mA | 7 |
| Output voltage | VOUT | 3.686 | 3.8 | 3.914 | V | IOUT = 1mA to 150mA, TJ = 25°C | 7 |
| Output voltage | VOUT | 3.667 | 3.8 | 3.933 | V | IOUT = 1mA to 150mA | 7 |
| Quiescent current (GND current) | IQ | 65 | 125 | µA | For new chip, IOUT = 0mA | 7 | |
| Quiescent current (GND current) | IQ | 765 | 890 | µA | For new chip, IOUT = 1mA to 150mA, TJ = 25°C | 7 | |
| Quiescent current (GND current) | IQ | 1060 | µA | For new chip, IOUT = 1mA to 150mA | 7 | ||
| Output voltage line regulation | ΔVOUT/VOUT | 0.01 | %/V | For new chip, VOUT(NOM) +1.0V ≤ VIN ≤ 10V, VIN ≥ 3.5V, TJ = 25°C | 7 | ||
| Output noise voltage | Vn | 165 | µVRMS | For new chip BW = 300Hz to 50kHz, VOUT = 3.3V, COUT = 4.7µF | 7 | ||
| Output current limit | ICL | 0.8 | 1.05 | A | For new chip VOUT = 0V | 7 | |
| Standby current | ISTANDBY | 1.25 | µA | For new chip EN < 0.15V, TJ = 25℃ | 8 | ||
| Standby current | ISTANDBY | 1.12 | 2.75 | µA | For new chip EN < 0.15V | 8 | |
| High level enable input voltage | EN | 0.85 | 1.6 | V | For new chip | 8 | |
| Low level enable input voltage | EN | 0.15 | 0.72 | V | For new chip | 8 | |
| Dropout voltage | VDO | 180 | 198 | mV | For new chip, IOUT = 150mA, TJ = 25°C | 9 | |
| Dropout voltage | VDO | 254 | mV | For new chip, IOUT = 150mA | 9 | ||
| Input voltage | VIN | 2.7 | 10 | V | 4 | ||
| Enable voltage (for new chip) | EN | 0 | 10 | V | 4 | ||
| Output voltage (for new chip) | VOUT | 1.2 | 6.5 | V | 4 | ||
| Output current | IOUT | 0 | 150 | mA | 4 | ||
| Output capacitance (for new chip) | COUT | 1 | 2.2 | 220 | µF | 4 | |
| Output capacitor ESR (for new chip) | COUT ESR | 0 | 1 | Ω | 4 | ||
| Input capacitance (for new chip) | CIN | 0.47 | µF | 4 | |||
| Junction temperature (for new chip) | TJ | -40 | 150 | °C | 4 | ||
| Input voltage (for new chip) | VIN | -0.3 | 18 | V | 4 | ||
| Output voltage | VOUT | -0.3 | 7 | V | 4 | ||
| Voltage range at EN (for new chip) | EN | -0.3 | 18 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance (new chip) | RθJA | 178.6 | °C/W | SOT-23 (DBV) 5 pins | 5 | ||
| Junction-to-case (top) thermal resistance (new chip) | RθJC(top) | 77.9 | °C/W | SOT-23 (DBV) 5 pins | 5 | ||
| Junction-to-board thermal resistance (new chip) | RθJB | 47.2 | °C/W | SOT-23 (DBV) 5 pins | 5 | ||
| Junction-to-top characterization parameter (new chip) | ΨJT | 15.9 | °C/W | SOT-23 (DBV) 5 pins | 5 | ||
| Junction-to-board characterization parameter (new chip) | ΨJB | 46.9 | °C/W | SOT-23 (DBV) 5 pins | 5 |
CAD (KiCad official)
- Symbol:
TPS76338DBVT - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps76338dbvt-etched.step/tps76338dbvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps76338dbvt.step/tps76338dbvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
127f071e72d70ec4, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).