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TPS76038DBVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 24d ago
viewers tps76038dbvr: viewers · Ray 24d ago
package.json Publish 0.1.0 · Ray 24d ago
page.json tps76038dbvr: specified limits as data (metadata.characteristics, 37 rows from the datasheet) · Ray 17d ago
README.md tps76038dbvr: specified limits as data (metadata.characteristics, 37 rows from the datasheet) · Ray 17d ago
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tps76038dbvr-etched.step tps76038dbvr: factory component page (tier=lcsc) · Ray 24d ago
tps76038dbvr-hero.glb tps76038dbvr: hero GLB from the etched model (keeps the MPN mark) · Ray 24d ago
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tps76038dbvr.glb Publish 0.1.0 · Ray 24d ago
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TPS76038DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS76038DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage pin; for the TPS76038 the recommended input is 4 V to 16 V, and the absolute input voltage range is -0.3 V to 16 V with respect to GND.
2 GND power_in Ground reference pin; all voltages are referenced to this device GND pin.
3 EN input Enable input; a logic low (0.8 V maximum) shuts the regulator off and reduces supply current to less than 1 µA, a logic high (2 V minimum) enables normal operation, and the pin must not be left floating.
4 NC unconnected No internal connection.
5 OUT power_out Regulated 3.8 V output for the TPS76038 at up to 50 mA; an output capacitor of at least 2.2 µF with ESR between 0.1 Ω and 20 Ω is required between OUT and GND for stability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage, TJ = 25°C VO 3.76 3.8 3.84 V TJ = 25°C 3
Output voltage, TJ = 25°C, 1 mA < IO < 50 mA VO 3.73 3.84 V TJ = 25°C, 1 mA < IO < 50 mA 3
Output voltage, 1 mA < IO < 50 mA VO 3.7 3.9 V 1 mA < IO < 50 mA 3
Standby current II(standby) 1 µA EN = 0 V 3
Quiescent current (GND current) 90 115 µA IO = 0 mA, TJ = 25°C 3
Quiescent current (GND current) 130 µA IO = 0 mA 3
Quiescent current (GND current) 100 130 µA IO = 1 mA, TJ = 25°C 3
Quiescent current (GND current) 170 µA IO = 1 mA 3
Quiescent current (GND current) 190 215 µA IO = 10 mA, TJ = 25°C 3
Quiescent current (GND current) 260 µA IO = 10 mA 3
Quiescent current (GND current) 850 1100 µA IO = 50 mA, TJ = 25°C 3
Quiescent current (GND current) 1200 µA IO = 50 mA 3
Input regulation 3 10 mV 4.8 V < VI < 16, IO = 1 mA 3
Peak output current / current limit 100 125 135 mA 3
High level enable input 2 V 3
Low level enable input 0.8 V 3
Input current (EN) II -1 0 1 µA EN = 0 V 3
Input current (EN) II 2.5 5 µA EN = VI 3
Dropout voltage VDO 1 3 mV IO = 0 mA, TJ = 25°C 3
Dropout voltage VDO 5 mV IO = 0 mA 3
Dropout voltage VDO 7 10 mV IO = 1 mA, TJ = 25°C 3
Dropout voltage VDO 15 mV IO = 1 mA 3
Dropout voltage VDO 40 60 mV IO = 10 mA, TJ = 25°C 3
Dropout voltage VDO 90 mV IO = 10 mA 3
Dropout voltage VDO 120 150 mV IO = 50 mA, TJ = 25°C 3
Dropout voltage VDO 180 mV IO = 50 mA 3
Input voltage range VI -0.3 16 V All voltages with respect to device GND pin 2
Voltage range at EN (maximum is VI + 0.3 V, not a fixed number) VEN -0.3 V Relative to VI 2
Operating junction temperature range TJ -40 150 °C 2
Storage temperature range Tstg -65 150 °C 2
ESD rating, HBM 1.5 kV Human body model 2
Input voltage, VI (TPS76038) VI 4 16 V TPS76038 2
Continuous output current IO 0 50 mA 2
Operating junction temperature TJ -40 125 °C 2
Junction-to-ambient thermal resistance (Low K board) RθJA 259 °C/W Low K JEDEC (1s) board 2
Junction-to-ambient thermal resistance (High K board) RθJA 180 °C/W High K JEDEC (2s2p) board 2
Junction-to-case thermal resistance RθJC 65.8 °C/W 2

CAD (KiCad official)

  • Symbol: TPS76038DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps76038dbvr-etched.step / tps76038dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps76038dbvr.step / tps76038dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 0307a6a83756359f, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF