main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 22d ago
viewers tps75425qpwpr: viewers · Ray 22d ago
package.json tps75425qpwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
page.json tps75425qpwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
README.md Publish 0.1.0 · Ray 22d ago
tps75425qpwpr-etched.glb tps75425qpwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps75425qpwpr-etched.step tps75425qpwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps75425qpwpr-hero.glb tps75425qpwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps75425qpwpr-hero.overlay.json tps75425qpwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps75425qpwpr.glb plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago
tps75425qpwpr.kicad_mod Publish 0.1.0 · Ray 22d ago
tps75425qpwpr.kicad_sym Publish 0.1.0 · Ray 22d ago
tps75425qpwpr.lbr Publish 0.1.0 · Ray 22d ago
tps75425qpwpr.step plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago

TPS75425QPWPR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP

TPS75425QPWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND/HEATSINK power_in Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it can be connected to GND or left floating.
2 NC unconnected Not connected.
3 IN power_in Regulator input voltage; absolute maximum input voltage range VIN is -0.3 to +6 V and an input bypass capacitor of 0.22 μF to 1 μF is recommended close to the input pins.
4 IN power_in Regulator input voltage; absolute maximum input voltage range VIN is -0.3 to +6 V and an input bypass capacitor of 0.22 μF to 1 μF is recommended close to the input pins.
5 EN input Negative polarity enable input: the device is enabled when EN is at logic low and shuts down at logic high, with an absolute maximum voltage range of -0.3 to +16.5 V.
6 RESET/PG output Open-drain power-good (PG) output for the TPS754xxQ, active high, going high-impedance when VOUT reaches 83% of its regulated voltage and requiring a pullup resistor; maximum PG voltage is 16.5 V.
7 FB/SENSE input Feedback input for the adjustable version, which must connect to an external resistor divider, or sense input for fixed-output versions, which must connect to the regulator output with the shortest possible connection.
8 OUTPUT power_out Regulated output voltage; an output capacitor of at least 47 μF with ESR between 100 mΩ and 10 Ω is required between OUT and GND for stability.
9 OUTPUT power_out Regulated output voltage; an output capacitor of at least 47 μF with ESR between 100 mΩ and 10 Ω is required between OUT and GND for stability.
10 GND/HEATSINK power_in Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it can be connected to GND or left floating.
11 GND/HEATSINK power_in Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it can be connected to GND or left floating.
12 NC unconnected Not connected.
13 NC unconnected Not connected.
14 NC unconnected Not connected.
15 NC unconnected Not connected.
16 NC unconnected Not connected.
17 GND power_in Ground reference for the regulator.
18 NC unconnected Not connected.
19 NC unconnected Not connected.
20 GND/HEATSINK power_in Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it can be connected to GND or left floating.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS75425QPWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps75425qpwpr-etched.step / tps75425qpwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps75425qpwpr.step / tps75425qpwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 ddac75f3b3fd04bf, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF