component
TPS75201QPWP
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 22d ago |
| viewers | 22d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 22d ago |
| tps75201qpwp-etched.glb | 16d ago |
| tps75201qpwp-etched.step | 16d ago |
| tps75201qpwp-hero.glb | 16d ago |
| tps75201qpwp-hero.overlay.json | 16d ago |
| tps75201qpwp.glb | 16d ago |
| tps75201qpwp.kicad_mod | 22d ago |
| tps75201qpwp.kicad_sym | 22d ago |
| tps75201qpwp.lbr | 22d ago |
| tps75201qpwp.step | 16d ago |
TPS75201QPWP
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20
TPS75201QPWP from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 2 | NC | unconnected | Not connected. |
| 3 | IN | power_in | Input voltage to the LDO; absolute maximum input voltage range is -0.3 V to +6 V, and a 0.22 µF to 1 µF input bypass capacitor is recommended as close to the input pins as possible. |
| 4 | IN | power_in | Input voltage to the LDO; absolute maximum input voltage range is -0.3 V to +6 V, and a 0.22 µF to 1 µF input bypass capacitor is recommended as close to the input pins as possible. |
| 5 | EN | input | Negative polarity enable input: the device is enabled when EN is at logic low and shut down when EN is at logic high; absolute maximum voltage at EN is -0.3 V to +16.5 V. |
| 6 | RESET/PG | output | On the TPS752xxQ this is an open-drain, active-low RESET output that goes high-impedance after a 100-ms delay when VOUT reaches 95% of its regulated value and goes low when VOUT falls below 95%; it requires a pullup resistor and its maximum voltage is 16.5 V. |
| 7 | FB/SENSE | input | Feedback input for the adjustable version (TPS75x01), which must connect to an external resistor divider with the connection kept as short as possible; the adjustable output range is 1.5 V to 5 V, and the absolute maximum voltage at OUT and FB is 5.5 V. |
| 8 | OUTPUT | power_out | Regulated output voltage; an output capacitor of at least 47 µF with ESR between 100 mΩ and 10 Ω must be connected between OUT and GND for stability, and the absolute maximum voltage at OUT is 5.5 V. |
| 9 | OUTPUT | power_out | Regulated output voltage; an output capacitor of at least 47 µF with ESR between 100 mΩ and 10 Ω must be connected between OUT and GND for stability, and the absolute maximum voltage at OUT is 5.5 V. |
| 10 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 11 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 12 | NC | unconnected | Not connected. |
| 13 | NC | unconnected | Not connected. |
| 14 | NC | unconnected | Not connected. |
| 15 | NC | unconnected | Not connected. |
| 16 | NC | unconnected | Not connected. |
| 17 | GND | power_in | Ground reference for the device; all voltages are referenced to network terminal ground. |
| 18 | NC | unconnected | Not connected. |
| 19 | NC | unconnected | Not connected. |
| 20 | GND/HEATSINK | power_in | Ground/heatsink terminal connected directly to the mount pad for thermal-enhanced operation; it may be connected to GND or left floating. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS75201QPWP - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps75201qpwp-etched.step/tps75201qpwp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps75201qpwp.step/tps75201qpwp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
ddac75f3b3fd04bf, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).