component
TPS74901RGWT
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS74901RGWT
Texas Instruments · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)
TPS74901RGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 2 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 3 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 4 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 5 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 6 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 7 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 8 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 9 | PG | output | Power-good (PG) is an open-drain, active-high output that indicates the status of VOUT; it requires a pullup resistor from 10kΩ to 1MΩ to a supply up to 5.5V. |
| 10 | BIAS | input | Bias input voltage for error amplifier, reference, and internal control circuits; it must be at least VOUT + VDO(VBIAS) and at least 2.7 V, with a maximum of 5.5 V. |
| 11 | EN | input | Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. |
| 12 | GND | power_in | Ground reference for the regulator. |
| 13 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 14 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 15 | SS | passive | Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 100µs. |
| 16 | FB | input | Feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. |
| 17 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 18 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 19 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 20 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy (RGW and SON packages), legacy chip | VOUT | -2 | 0.5 | 2 | % | VOUT + 2.2V ≤ VBIAS ≤ 5.5 V, 50mA ≤ IOUT ≤ 3A (Legacy Chip) | 5 |
| Output voltage accuracy (RGW and SON packages), new chip | VOUT | -1 | 0.3 | 1 | % | VOUT + 2.2V ≤ VBIAS ≤ 5.5V, 50mA ≤ IOUT ≤ 3A (New Chip) | 5 |
| VIN dropout voltage, legacy chip | VDO | 120 | 280 | mV | IOUT = 3A, VBIAS, VOUT(nom) ≥ 3.25V (Legacy Chip) | 5 | |
| VIN dropout voltage, new chip | VDO | 120 | 200 | mV | IOUT = 3A, VBIAS, VOUT(nom) ≥ 3.25V (New Chip) | 5 | |
| VBIAS dropout voltage, legacy chip | 1.31 | 1.75 | V | IOUT = 3A, VIN = VBIAS (Legacy Chip) | 5 | ||
| VBIAS dropout voltage, new chip | 1.45 | 1.6 | V | IOUT = 3A, VIN = VBIAS (New Chip) | 5 | ||
| Current limit, RGW package | ICL | 3.9 | 4.6 | 5.5 | A | VOUT = 80% × VOUT(nom), RGW Package | 5 |
| BIAS pin current, legacy chip | IBIAS | 1 | 2 | mA | Legacy Chip | 5 | |
| BIAS pin current, new chip | IBIAS | 1 | 1.2 | mA | New Chip | 5 | |
| Shutdown supply current (IGND), legacy chip | ISHDN | 1 | 50 | µA | VEN ≤ 0.4V (Legacy Chip) | 5 | |
| Shutdown supply current (IGND), new chip | ISHDN | 0.85 | 2.75 | µA | VEN ≤ 0.4V, VIN = VBIAS = 5.5V (New Chip) | 5 | |
| Feedback pin current, legacy chip | IFB | -1 | 0.15 | 1 | µA | Legacy Chip | 6 |
| Feedback pin current, new chip | IFB | -30 | 0.15 | 30 | nA | New Chip | 6 |
| Enable input high level | VEN(hi) | 1.1 | 5.5 | V | 6 | ||
| Enable input low level | VEN(lo) | 0 | 0.4 | V | 6 | ||
| Enable pin current, legacy chip | IEN | 0.1 | 1 | µA | VEN = 5V (Legacy Chip) | 6 | |
| Enable pin current, new chip | IEN | 0.1 | 0.25 | µA | VEN = 5V (New Chip) | 6 | |
| PG trip threshold | VIT | 85 | 90 | 94 | %VOUT | VOUT decreasing | 6 |
| PG output low voltage, legacy chip | VPG(lo) | 0.3 | V | IPG = 1mA (sinking), VOUT < VIT (Legacy Chip) | 6 | ||
| PG output low voltage, new chip | VPG(lo) | 0.12 | V | IPG = 1mA (sinking), VOUT < VIT (New Chip) | 6 | ||
| PG leakage current, legacy chip | IPG(lkg) | 0.1 | 1 | µA | VPG = 5.25V, VOUT > VIT (Legacy Chip) | 6 | |
| PG leakage current, new chip | IPG(lkg) | 0.001 | 0.05 | µA | VPG = 5.25V, VOUT > VIT (New Chip) | 6 | |
| Operating junction temperature | TJ | -40 | 125 | ℃ | 6 | ||
| Thermal shutdown temperature, shutdown (temperature increasing) | TSD | 165 | ℃ | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown temperature, reset (temperature decreasing) | TSD | 140 | ℃ | Reset, temperature decreasing | 6 | ||
| Input supply voltage | VIN | 5.5 | V | VOUT + VDO (VIN) to 5.5 V | 4 | ||
| Enable supply voltage | VEN | 5.5 | V | 4 | |||
| BIAS supply voltage | VBIAS | 5.5 | V | VOUT + VDO (VBIAS) to 5.5 V; BIAS supply required when VIN is below VOUT + 1.62 V | 4 | ||
| Output voltage | VOUT | 0.8 | 3.6 | V | 4 | ||
| Output current | IOUT | 0 | 3 | A | 4 | ||
| Output capacitor | COUT | 2.2 | µF | 4 | |||
| Input capacitor | CIN | 1 | µF | 4 | |||
| Bias capacitor | CBIAS | 0.1 | 1 | µF | 4 | ||
| VIN, VBIAS input voltage | VIN, VBIAS | -0.3 | 6 | V | 4 | ||
| Enable voltage | VEN | -0.3 | 6 | V | 4 | ||
| Power-good voltage | VPG | -0.3 | 6 | V | 4 | ||
| PG sink current | IPG | 0 | 1.5 | mA | 4 | ||
| Soft-start voltage | VSS | -0.3 | 6 | V | 4 | ||
| Feedback voltage | VFB | -0.3 | 6 | V | 4 | ||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance, RGW (VQFN), 20 pins | RθJA | 38.1 | °C/W | RGW (VQFN) 20 pins | 5 | ||
| Junction-to-ambient thermal resistance, RGW (VQFN), new chip | RθJA | 34.7 | °C/W | RGW (VQFN) (2) New Chip | 5 | ||
| Junction-to-case (top) thermal resistance, RGW (VQFN) | RθJC(top) | 36.3 | °C/W | RGW (VQFN) 20 pins | 5 | ||
| Junction-to-board thermal resistance, RGW (VQFN) | RθJB | 17.5 | °C/W | RGW (VQFN) 20 pins | 5 | ||
| Junction-to-case (bottom) thermal resistance, RGW (VQFN) | RθJC(bot) | 6.2 | °C/W | RGW (VQFN) 20 pins | 5 |
CAD (KiCad official)
- Symbol:
TPS74901RGWT - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps74901rgwt-etched.step/tps74901rgwt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps74901rgwt.step/tps74901rgwt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (47 pp, sha256
bf8af2cd98671dc1, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS74901RGWT
**Texas Instruments** · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)
TPS74901RGWT from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 2 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 3 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 4 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 5 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 6 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 7 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 8 | IN | input | Unregulated input to the device; the recommended input supply voltage is up to 5.5 V and the absolute maximum is 6 V. |
| 9 | PG | output | Power-good (PG) is an open-drain, active-high output that indicates the status of VOUT; it requires a pullup resistor from 10kΩ to 1MΩ to a supply up to 5.5V. |
| 10 | BIAS | input | Bias input voltage for error amplifier, reference, and internal control circuits; it must be at least VOUT + VDO(VBIAS) and at least 2.7 V, with a maximum of 5.5 V. |
| 11 | EN | input | Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. |
| 12 | GND | power_in | Ground reference for the regulator. |
| 13 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 14 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 15 | SS | passive | Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 100µs. |
| 16 | FB | input | Feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. |
| 17 | NC | unconnected | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| 18 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 19 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 20 | OUT | output | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2µF, ceramic) is needed from this pin to ground to assure stability. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy (RGW and SON packages), legacy chip | VOUT | -2 | 0.5 | 2 | % | VOUT + 2.2V ≤ VBIAS ≤ 5.5 V, 50mA ≤ IOUT ≤ 3A (Legacy Chip) | 5 |
| Output voltage accuracy (RGW and SON packages), new chip | VOUT | -1 | 0.3 | 1 | % | VOUT + 2.2V ≤ VBIAS ≤ 5.5V, 50mA ≤ IOUT ≤ 3A (New Chip) | 5 |
| VIN dropout voltage, legacy chip | VDO | | 120 | 280 | mV | IOUT = 3A, VBIAS, VOUT(nom) ≥ 3.25V (Legacy Chip) | 5 |
| VIN dropout voltage, new chip | VDO | | 120 | 200 | mV | IOUT = 3A, VBIAS, VOUT(nom) ≥ 3.25V (New Chip) | 5 |
| VBIAS dropout voltage, legacy chip | | | 1.31 | 1.75 | V | IOUT = 3A, VIN = VBIAS (Legacy Chip) | 5 |
| VBIAS dropout voltage, new chip | | | 1.45 | 1.6 | V | IOUT = 3A, VIN = VBIAS (New Chip) | 5 |
| Current limit, RGW package | ICL | 3.9 | 4.6 | 5.5 | A | VOUT = 80% × VOUT(nom), RGW Package | 5 |
| BIAS pin current, legacy chip | IBIAS | | 1 | 2 | mA | Legacy Chip | 5 |
| BIAS pin current, new chip | IBIAS | | 1 | 1.2 | mA | New Chip | 5 |
| Shutdown supply current (IGND), legacy chip | ISHDN | | 1 | 50 | µA | VEN ≤ 0.4V (Legacy Chip) | 5 |
| Shutdown supply current (IGND), new chip | ISHDN | | 0.85 | 2.75 | µA | VEN ≤ 0.4V, VIN = VBIAS = 5.5V (New Chip) | 5 |
| Feedback pin current, legacy chip | IFB | -1 | 0.15 | 1 | µA | Legacy Chip | 6 |
| Feedback pin current, new chip | IFB | -30 | 0.15 | 30 | nA | New Chip | 6 |
| Enable input high level | VEN(hi) | 1.1 | | 5.5 | V | | 6 |
| Enable input low level | VEN(lo) | 0 | | 0.4 | V | | 6 |
| Enable pin current, legacy chip | IEN | | 0.1 | 1 | µA | VEN = 5V (Legacy Chip) | 6 |
| Enable pin current, new chip | IEN | | 0.1 | 0.25 | µA | VEN = 5V (New Chip) | 6 |
| PG trip threshold | VIT | 85 | 90 | 94 | %VOUT | VOUT decreasing | 6 |
| PG output low voltage, legacy chip | VPG(lo) | | | 0.3 | V | IPG = 1mA (sinking), VOUT < VIT (Legacy Chip) | 6 |
| PG output low voltage, new chip | VPG(lo) | | | 0.12 | V | IPG = 1mA (sinking), VOUT < VIT (New Chip) | 6 |
| PG leakage current, legacy chip | IPG(lkg) | | 0.1 | 1 | µA | VPG = 5.25V, VOUT > VIT (Legacy Chip) | 6 |
| PG leakage current, new chip | IPG(lkg) | | 0.001 | 0.05 | µA | VPG = 5.25V, VOUT > VIT (New Chip) | 6 |
| Operating junction temperature | TJ | -40 | | 125 | ℃ | | 6 |
| Thermal shutdown temperature, shutdown (temperature increasing) | TSD | | 165 | | ℃ | Shutdown, temperature increasing | 6 |
| Thermal shutdown temperature, reset (temperature decreasing) | TSD | | 140 | | ℃ | Reset, temperature decreasing | 6 |
| Input supply voltage | VIN | | | 5.5 | V | VOUT + VDO (VIN) to 5.5 V | 4 |
| Enable supply voltage | VEN | | | 5.5 | V | | 4 |
| BIAS supply voltage | VBIAS | | | 5.5 | V | VOUT + VDO (VBIAS) to 5.5 V; BIAS supply required when VIN is below VOUT + 1.62 V | 4 |
| Output voltage | VOUT | 0.8 | | 3.6 | V | | 4 |
| Output current | IOUT | 0 | | 3 | A | | 4 |
| Output capacitor | COUT | 2.2 | | | µF | | 4 |
| Input capacitor | CIN | 1 | | | µF | | 4 |
| Bias capacitor | CBIAS | 0.1 | | 1 | µF | | 4 |
| VIN, VBIAS input voltage | VIN, VBIAS | -0.3 | | 6 | V | | 4 |
| Enable voltage | VEN | -0.3 | | 6 | V | | 4 |
| Power-good voltage | VPG | -0.3 | | 6 | V | | 4 |
| PG sink current | IPG | 0 | | 1.5 | mA | | 4 |
| Soft-start voltage | VSS | -0.3 | | 6 | V | | 4 |
| Feedback voltage | VFB | -0.3 | | 6 | V | | 4 |
| Junction temperature | TJ | -40 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 4 |
| Junction-to-ambient thermal resistance, RGW (VQFN), 20 pins | RθJA | | 38.1 | | °C/W | RGW (VQFN) 20 pins | 5 |
| Junction-to-ambient thermal resistance, RGW (VQFN), new chip | RθJA | | 34.7 | | °C/W | RGW (VQFN) (2) New Chip | 5 |
| Junction-to-case (top) thermal resistance, RGW (VQFN) | RθJC(top) | | 36.3 | | °C/W | RGW (VQFN) 20 pins | 5 |
| Junction-to-board thermal resistance, RGW (VQFN) | RθJB | | 17.5 | | °C/W | RGW (VQFN) 20 pins | 5 |
| Junction-to-case (bottom) thermal resistance, RGW (VQFN) | RθJC(bot) | | 6.2 | | °C/W | RGW (VQFN) 20 pins | 5 |
## CAD (KiCad official)
- Symbol: `TPS74901RGWT`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm`
- 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `tps74901rgwt-etched.step` / `tps74901rgwt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps74901rgwt.step` / `tps74901rgwt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps74901.pdf) (47 pp, sha256 `bf8af2cd98671dc1`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps74901rgwt-datasheet.pdf)