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TPS74634PQWDRBRQ1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps74634pqwdrbrq1factory-2.0.0extractor-text

Verified TPS74634PQWDRBRQ1

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 9 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS74634PQWDRBRQ1 · SON-8-EP(3x3) · 9 pins
  • ✓copper: 9 copper pads, none touching another net
  • ✓datasheet: all 9 pin names found in the 48-page datasheet
  • ✓distributor: lcsc C2878102, digikey 296-TPS74634PQWDRBRQ1TR-ND, mouser 595-S74634PQWDRBRQ1
  • ✓family: WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_ek9aoya/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 9 pins = 9 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 9 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps74634pqwdrbrq1.kicad_sym✓ tps74634pqwdrbrq1.kicad_mod✓ tps74634pqwdrbrq1.step
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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3h ago
viewers tps74634pqwdrbrq1: viewers · Ray 3h ago
package.json Publish 0.1.0 · Ray 3h ago
page.json Set visibility: public · Ray 3h ago
README.md Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1-etched.glb Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1-etched.step tps74634pqwdrbrq1: factory component page (tier=mfr) · Ray 3h ago
tps74634pqwdrbrq1-hero.glb tps74634pqwdrbrq1: hero GLB from the etched model (keeps the MPN mark) · Ray 3h ago
tps74634pqwdrbrq1-hero.overlay.json Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1.glb Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1.kicad_mod Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1.kicad_sym Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1.lbr Publish 0.1.0 · Ray 3h ago
tps74634pqwdrbrq1.step Publish 0.1.0 · Ray 3h ago
verification.json Verified: Published by the parts factory: tier mfr, 9 pins · Ray 2h ago

TPS74634PQWDRBRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SON-8-EP(3x3)

TPS74634PQWDRBRQ1 from Texas Instruments, in a SON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage pin; a ceramic output capacitor from OUT to ground is required for stability, with COUT of 1 µF to 220 µF per the recommended operating conditions.
2 NC unconnected No internal connection; ground this pin for better thermal performance.
3 NC unconnected No internal connection; ground this pin for better thermal performance.
4 GND power_in Ground pin.
5 EN input Enable pin; drive EN greater than VEN(HI) to turn on the regulator and less than VEN(LO) to put the LDO into shutdown, with VEN rated 0 V to 6.0 V.
6 PG output Power-good output available in open-drain or push-pull topology, with a pullup resistor required for the open-drain version and VPG rated 0 V to 6.0 V.
7 NC unconnected No internal connection; ground this pin for better thermal performance.
8 IN power_in Input pin; use the recommended or larger ceramic capacitor from IN to ground, with VIN rated 1.5 V to 6.0 V.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SON-8-EP(3x3)
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VIN -0.3 6.5 V 4
Enable voltage VEN -0.3 6.5 V 4
Power-good voltage VPG -0.3 6.5 V 4
Output voltage VOUT -0.3 V max printed as VIN + 0.3 V (or 6.0 V, whichever is smaller) 4
Power-good current IPG -10 10 mA 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input voltage VIN 1.5 6 V 4
Output voltage, fixed version VOUT 0.65 5 V fixed version 4
Output current IOUT 0 1 A 4
Input capacitor CIN 1 µF 4
Output capacitor COUT 1 220 µF minimum derated capacitance 0.47 µF required for stability 4
Enable voltage VEN 0 6 V 4
Enable toggle frequency fEN 10 kHz 4
PG voltage VPG 0 6 V 4
Junction temperature TJ -40 150 °C 4
Output accuracy -0.85 0.85 % TJ = 25°C 5
Output accuracy -1 1 % -40°C ≤ TJ ≤ 85°C 5
Output accuracy -1.5 1.5 % -40°C ≤ TJ ≤ 150°C 5
Line regulation 2 7.5 mV VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.0 V 5
Ground current IGND 25 32 µA IOUT = 0 mA, TJ = 25°C 5
Ground current IGND 25 36 µA IOUT = 0 mA, -40°C ≤ TJ ≤ 150°C 5
Shutdown current ISHDN 0.1 1 µA VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V, -40°C ≤ TJ ≤ 125°C 5
Shutdown current ISHDN 0.1 1.55 µA VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V, -40°C ≤ TJ ≤ 150°C 5
Dropout voltage VDO 160 265 mV 3.3 V ≤ VOUT ≤ 5.5 V; IOUT = 1 A, VOUT = 0.95 x VOUT(NOM) 5
Undervoltage lockout rising VUVLO 1.21 1.33 1.47 V VIN rising 6
Undervoltage lockout falling VUVLO 1.17 1.29 1.42 V VIN falling 6
Startup time tSTR 200 500 650 µs From EN low-to-high transition to VOUT = VOUT(NOM) x 95% 6
PG high threshold PGHTH 89 92 96 %VOUT VOUT increasing 6
PG low threshold PGLTH 86 90 93 %VOUT VOUT decreasing 6
PG pin leakage current Ilkg(PG) 7 50 nA VOUT > PGHTH, VPG = 6.0 V 6
PG delay time rising tPGDH 135 165 178 µs output overdrive = 10% 6
PG delay time falling tPGDL 1.5 7 10 µs time from 90% VOUT to 80% of PG 6
Junction-to-ambient thermal resistance RθJA 55.5 °C/W DRB (8-pin VSON) 5
Junction-to-case (top) thermal resistance RθJC(top) 70.7 °C/W DRB (8-pin VSON) 5
Junction-to-board thermal resistance RθJB 28 °C/W DRB (8-pin VSON) 5
Junction-to-top characterization parameter ψJT 4.3 °C/W DRB (8-pin VSON) 5
Junction-to-board characterization parameter ψJB 28 °C/W DRB (8-pin VSON) 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 10.2 °C/W DRB (8-pin VSON) 5

CAD (KiCad official)

  • Symbol: TPS74634PQWDRBRQ1
  • Footprint: Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm
  • 3D model: SON-8-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps74634pqwdrbrq1-etched.step / tps74634pqwdrbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps74634pqwdrbrq1.step / tps74634pqwdrbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 184c3108e6b0527b, retrieved 2026-11-05, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF