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TPS74529PQWDRVRQ1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS74529PQWDRVRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS74529PQWDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Regulated output voltage pin that requires a capacitor from OUT to ground for stability, with a 1 µF or larger ceramic capacitor recommended and placed as close to the device as possible (COUT range 1 µF to 220 µF, with at least 0.47 µF derated capacitance required).
2 NC unconnected No internal connection; the datasheet says to ground this pin for better thermal performance.
3 GND power_in Ground pin, electrically connected to the thermal pad, which should be connected to the GND plane for improved thermal performance.
4 EN input Enable pin: drive above VEN(HI) to turn on the regulator and below VEN(LO) to put the LDO into shutdown; the recommended enable voltage range is 0 V to 6.0 V.
5 PG output Power-good output (open-drain on this variant); a pull-up resistor is required for the open-drain type, the absolute maximum power-good current is ±10 mA, and the recommended PG voltage range is 0 V to 6.0 V.
6 IN power_in Input pin supplying the LDO; use the recommended 1 µF or larger ceramic capacitor from IN to ground, placed as close to the device as possible, with a recommended input voltage range of 1.5 V to 6.0 V.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VIN VIN -0.3 6.5 V 4
Enable voltage VEN -0.3 6.5 V 4
Power-good voltage VPG -0.3 6.5 V 4
Output voltage VOUT -0.3 V Max printed as VIN + 0.3; footnote (2): absolute maximum is VIN + 0.3 V or 6.0 V, whichever is smaller 4
Power-good current IPG -10 10 mA Printed as ±10 mA 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Input voltage VIN 1.5 6 V 4
Output voltage (fixed only) VOUT 0.65 5 V Fixed only 4
Output current IOUT 0 500 mA 4
Output capacitor COUT 1 220 µF Footnote (1): minimum derated capacitance of 0.47 µF is required for stability 4
Enable voltage VEN 0 6 V 4
PG voltage VPG 0 6 V 4
Junction operating temperature TJ -40 150 °C 4
Output accuracy -0.85 0.85 % TJ = 25°C; external resistor tolerances not included 5
Output accuracy -1 1 % -40°C ≤ TJ ≤ 85°C; external resistor tolerances not included 5
Output accuracy -1.5 1.5 % -40°C ≤ TJ ≤ 150°C; external resistor tolerances not included 5
Line regulation 2 7.5 mV VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.0 V 5
Ground current IGND 25 32 µA IOUT = 0 mA, TJ = 25°C 5
Ground current IGND 25 36 µA IOUT = 0 mA, -40°C ≤ TJ ≤ 150°C 5
Shutdown current ISHDN 0.1 1 µA VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V, -40°C ≤ TJ ≤ 125°C 5
Shutdown current ISHDN 0.1 1.55 µA VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V, -40°C ≤ TJ ≤ 150°C 5
Output current limit ICL 515 720 865 mA VOUT(NOM) ≥ 1.0 V, VOUT = VOUT(NOM) x 0.85, VIN = VOUT(NOM) + 1.0 V 5
Short-circuit current limit ISC 200 350 400 mA VOUT = 0 V; VOUT(NOM) ≥ 1.0 V, VIN = VOUT(NOM) + 1.0 V 5
Dropout voltage VDO 105 170 mV IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 2.5 V ≤ VOUT < 3.3 V 5
Undervoltage lockout, VIN falling VUVLO 1.17 1.3 1.42 V VIN falling 5
Undervoltage lockout, VIN rising VUVLO 1.21 1.34 1.47 V VIN rising 5
Startup time tSTR 200 500 650 µs From EN low-to-high transition to VOUT = VOUT(NOM) x 0.95 6
EN pin low voltage (disabled) VEN(LO) 0.3 V 6
PG high threshold PGHTH 89 92 96 %VOUT VOUT increasing 6
PG low threshold PGLTH 86 90 93 %VOUT VOUT decreasing 6
PG pin leakage current Ilkg(PG) 7 50 nA VOUT > PGHTH, VPG = 6.0 V; open-drain version only 6
PG delay time rising tPGDH 135 165 178 µs Time from 92% VOUT to 20% of PG; output overdrive = 10% 6
PG delay time falling tPGDL 1.5 7 10 µs Time from 90% VOUT to 80% of PG; output overdrive = 10% 6
Junction-to-ambient thermal resistance (DRV, WSON) RθJA 80.3 °C/W DRV (6-pin WSON) package 5
Junction-to-case (top) thermal resistance (DRV, WSON) RθJC(top) 98.7 °C/W DRV (6-pin WSON) package 5
Junction-to-board thermal resistance (DRV, WSON) RθJB 44.8 °C/W DRV (6-pin WSON) package 5
Junction-to-top characterization parameter (DRV, WSON) ψJT 6.1 °C/W DRV (6-pin WSON) package 5
Junction-to-board characterization parameter (DRV, WSON) ψJB 45 °C/W DRV (6-pin WSON) package 5
Junction-to-case (bottom) thermal resistance (DRV, WSON) RθJC(bot) 20.8 °C/W DRV (6-pin WSON) package 5

CAD (KiCad official)

  • Symbol: TPS74529PQWDRVRQ1
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps74529pqwdrvrq1-etched.step / tps74529pqwdrvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps74529pqwdrvrq1.step / tps74529pqwdrvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 434ed7c32560a28e, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF