Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TPS74525PQWDRVRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS74525PQWDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated 2.5 V output pin. Requires a ceramic capacitor to GND for stability (1 uF nominal, up to 220 uF; minimum derated 0.47 uF). Place COUT as close to the pin as possible; output range for fixed variants is 0.65 V to 5.0 V (this SKU is 2.5 V). Includes active discharge when disabled.
2 NC unconnected No internal connection on the fixed-output DRV variant (FB is not brought out because the resistor divider is internal). Ground this pin for better thermal performance.
3 GND power_in Device ground / return. Tie to the ground plane; the thermal pad is electrically connected to this GND node internally.
4 EN input Enable input. Drive above VEN(HI) to turn the LDO on, below VEN(LO) for shutdown mode (IQ ~1.5 uA). Absolute max -0.3 V to +6.5 V; recommended 0 V to 6.0 V. Toggle frequency limited to 10 kHz. Do not leave floating.
5 PG output Power-good output. This orderable (P suffix) is the push-pull option, so no pullup resistor is required. Asserts to indicate the internal feedback node has reached its regulation threshold. Absolute max PG current +/-10 mA; if unused, leave floating.
6 IN power_in Regulator input supply, 1.5 V to 6.0 V (abs max 6.5 V). Requires >=1 uF ceramic input capacitor placed close to the pin for best transient response and low input impedance.
7 GND (Thermal Pad) passive Exposed thermal pad on the bottom of the WSON package. Electrically connected to the GND node internally; connect to the PCB GND plane with multiple vias for improved thermal performance (RθJA = 80.3 °C/W for DRV).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Ordering variants

Same part, different packaging or reel option.

  • TPS74525PQWDRVRQ1
  • TPS74525PQWDRVRQ1DRVT
  • TPS74525PQWDRVRQ1DRBR
  • TPS74525PQWDRVRQ1DRBT

CAD (KiCad official)

  • Symbol: TPS74525PQWDRVRQ1
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps74525pqwdrvrq1-etched.step / tps74525pqwdrvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps74525pqwdrvrq1.step / tps74525pqwdrvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 434ed7c32560a28e, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF