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TPS74301RGWR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS74301RGWR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VQFN-20-EP(5x5)

TPS74301RGWR from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage; the new-silicon device requires an output capacitor of 2.2 µF or greater for stability, and the adjustable output range is 0.8 V to 3.6 V.
2 NC unconnected No internal connection; may be left floating or connected to GND for better thermal contact to the top plane.
3 NC unconnected No internal connection; may be left floating or connected to GND for better thermal contact to the top plane.
4 NC unconnected No internal connection; may be left floating or connected to GND for better thermal contact to the top plane.
5 IN power_in Unregulated input voltage; the recommended range is VOUT + VDO(VIN) to 5.5 V, and at least 1 µF of input capacitance is required.
6 IN power_in Unregulated input voltage; the recommended range is VOUT + VDO(VIN) to 5.5 V, and at least 1 µF of input capacitance is required.
7 IN power_in Unregulated input voltage; the recommended range is VOUT + VDO(VIN) to 5.5 V, and at least 1 µF of input capacitance is required.
8 IN power_in Unregulated input voltage; the recommended range is VOUT + VDO(VIN) to 5.5 V, and at least 1 µF of input capacitance is required.
9 PG output Open-drain, active-high power-good output that indicates VOUT status; it needs a 10 kΩ to 1 MΩ pull-up to a supply of up to 5.5 V, and it may be left floating if output monitoring is not needed.
10 BIAS input Bias input voltage for the error amplifier, reference and internal control circuitry; the recommended range is VOUT + VDO(VBIAS) to 5.5 V, with a 0.1 µF to 1 µF bias capacitor (CBIAS).
11 EN input Enable pin, active high: driving it above 1.1 V enables the regulator, below 0.4 V puts it in shutdown, and it must not be left floating (maximum 5.5 V).
12 GND power_in Ground reference for the device.
13 NC unconnected No internal connection; may be left floating or connected to GND for better thermal contact to the top plane.
14 NC unconnected No internal connection; may be left floating or connected to GND for better thermal contact to the top plane.
15 TRACK input Tracking pin: connect to the center tap of a resistor divider from an external supply so that OUT tracks it; the FB pin is regulated to TRACK while TRACK is below 0.8 V.
16 FB input Feedback connection to the center tap of the external resistor divider that sets the output voltage (0.8 V reference); it must not be left floating.
17 NC unconnected No internal connection; may be left floating or connected to GND for better thermal contact to the top plane.
18 OUT power_out Regulated output voltage; the new-silicon device requires an output capacitor of 2.2 µF or greater for stability, and the adjustable output range is 0.8 V to 3.6 V.
19 OUT power_out Regulated output voltage; the new-silicon device requires an output capacitor of 2.2 µF or greater for stability, and the adjustable output range is 0.8 V to 3.6 V.
20 OUT power_out Regulated output voltage; the new-silicon device requires an output capacitor of 2.2 µF or greater for stability, and the adjustable output range is 0.8 V to 3.6 V.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-20-EP(5x5)
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS74301RGWR
  • Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
  • 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps74301rgwr-etched.step / tps74301rgwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps74301rgwr.step / tps74301rgwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 de9667272db70c1d, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF