component
TPS74012DGKT
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS74012DGKT
Texas Instruments · Linear Voltage Regulators (LDO) · VSSOP-8
TPS74012DGKT from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin on the fixed output voltage version: driving it high enables the regulator, driving it low puts the regulator into shutdown, and it must not be left unconnected. |
| 2 | BIAS | power_in | Bias input voltage for the error amplifier, reference, and internal control circuits (VBIAS 2.9 V to 6.0 V per Features). |
| 3 | IN | power_in | Input to the device (VIN 1.2 V to 6.0 V per Features). |
| 4 | OUT | power_out | Regulated output voltage; a total typical capacitance of at least 2.2 µF (ceramic) to ground is needed for stability. |
| 5 | GND | power_in | Ground. |
| 6 | GND | power_in | Ground. |
| 7 | GND | power_in | Ground. |
| 8 | GND | power_in | Ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.2 | 6 | V | 4 | ||
| Bias pin voltage range | VBIAS | 2.9 | 6 | V | 4 | ||
| VOUT accuracy | VOUT | -1 | 1 | % | TJ = 25°C | 4 | |
| VOUT accuracy over temperature | VOUT | -2 | 2 | % | TJ = -40°C to +125°C | 4 | |
| Line regulation | ΔVOUT/ΔVIN | -0.1 | 0.01 | 0.1 | %/V | VIN = VOUT + 1 V to 6.0 V | 4 |
| Load regulation | ΔVOUT/ΔIOUT | 1.5 | % | ILOAD = 0 mA to 1.5 A (fixed output: 50 mA to 1.5 A) | 4 | ||
| VIN dropout voltage | VDO | 100 | 300 | mV | ILOAD = 1.5 A | 4 | |
| VBIAS dropout voltage | VDO | 1.3 | 1.6 | V | ILOAD = 1.5 A, VIN = VBIAS | 4 | |
| Ground pin current | IGND | 2 | 3 | mA | ILOAD = 1.5 A | 4 | |
| Shutdown supply current | ISHDN | 1 | 5 | μA | Fixed output version only. VEN ≤ 0.4 V, TJ = -40°C to +85°C, VOUT = 0 V | 4 | |
| Bias pin current | IBIAS | 2 | mA | ILOAD = 1.5 A | 4 | ||
| Current limit | ICL | 1.6 | 6 | A | VOUT = 80% × VOUT(NOM) | 4 | |
| Enable input high level | VEN,HI | 1.1 | 6 | V | 4 | ||
| Enable input low level | VEN,LO | 0 | 0.4 | V | RLOAD = 1 kΩ to GND | 4 | |
| Enable pin current | IEN | 0.1 | 1 | μA | VEN = 1.5 V | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Thermal shutdown temperature (shutdown) | TSD | 165 | °C | Shutdown, temperature increasing | 4 | ||
| Thermal shutdown temperature (reset) | TSD | 140 | °C | Reset, temperature decreasing | 4 | ||
| IN, BIAS voltage | -0.3 | 6.5 | V | 2 | |||
| EN, FB, OUT voltage | -0.3 | 6 | V | VBIAS + 0.3 V or +6.0 V, whichever is smaller | 2 | ||
| ESD HBM | 2 | kV | JESD22-A114A | 2 | |||
| ESD CDM | 500 | V | JESD22-C101B.01 | 2 | |||
| Junction-to-ambient thermal resistance | θJA | 136.9 | °C/W | DGK, 8 pins (TPS74001DGK column) | 3 | ||
| Junction-to-case (top) thermal resistance | θJCtop | 35.3 | °C/W | DGK, 8 pins | 3 | ||
| Junction-to-board thermal resistance | θJB | 68 | °C/W | DGK, 8 pins | 3 | ||
| Junction-to-top characterization parameter | ψJT | 0.9 | °C/W | DGK, 8 pins | 3 | ||
| Junction-to-board characterization parameter | ψJB | 67.8 | °C/W | DGK, 8 pins | 3 |
CAD (KiCad official)
- Symbol:
TPS74012DGKT - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
tps74012dgkt-etched.step/tps74012dgkt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps74012dgkt.step/tps74012dgkt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
ed37adf4d937b6d9, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS74012DGKT
**Texas Instruments** · Linear Voltage Regulators (LDO) · VSSOP-8
TPS74012DGKT from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable pin on the fixed output voltage version: driving it high enables the regulator, driving it low puts the regulator into shutdown, and it must not be left unconnected. |
| 2 | BIAS | power_in | Bias input voltage for the error amplifier, reference, and internal control circuits (VBIAS 2.9 V to 6.0 V per Features). |
| 3 | IN | power_in | Input to the device (VIN 1.2 V to 6.0 V per Features). |
| 4 | OUT | power_out | Regulated output voltage; a total typical capacitance of at least 2.2 µF (ceramic) to ground is needed for stability. |
| 5 | GND | power_in | Ground. |
| 6 | GND | power_in | Ground. |
| 7 | GND | power_in | Ground. |
| 8 | GND | power_in | Ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | Power Supply Chip |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.2 | | 6 | V | | 4 |
| Bias pin voltage range | VBIAS | 2.9 | | 6 | V | | 4 |
| VOUT accuracy | VOUT | -1 | | 1 | % | TJ = 25°C | 4 |
| VOUT accuracy over temperature | VOUT | -2 | | 2 | % | TJ = -40°C to +125°C | 4 |
| Line regulation | ΔVOUT/ΔVIN | -0.1 | 0.01 | 0.1 | %/V | VIN = VOUT + 1 V to 6.0 V | 4 |
| Load regulation | ΔVOUT/ΔIOUT | | | 1.5 | % | ILOAD = 0 mA to 1.5 A (fixed output: 50 mA to 1.5 A) | 4 |
| VIN dropout voltage | VDO | | 100 | 300 | mV | ILOAD = 1.5 A | 4 |
| VBIAS dropout voltage | VDO | | 1.3 | 1.6 | V | ILOAD = 1.5 A, VIN = VBIAS | 4 |
| Ground pin current | IGND | | 2 | 3 | mA | ILOAD = 1.5 A | 4 |
| Shutdown supply current | ISHDN | | 1 | 5 | μA | Fixed output version only. VEN ≤ 0.4 V, TJ = -40°C to +85°C, VOUT = 0 V | 4 |
| Bias pin current | IBIAS | | | 2 | mA | ILOAD = 1.5 A | 4 |
| Current limit | ICL | | 1.6 | 6 | A | VOUT = 80% × VOUT(NOM) | 4 |
| Enable input high level | VEN,HI | 1.1 | | 6 | V | | 4 |
| Enable input low level | VEN,LO | 0 | | 0.4 | V | RLOAD = 1 kΩ to GND | 4 |
| Enable pin current | IEN | | 0.1 | 1 | μA | VEN = 1.5 V | 4 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 4 |
| Thermal shutdown temperature (shutdown) | TSD | | 165 | | °C | Shutdown, temperature increasing | 4 |
| Thermal shutdown temperature (reset) | TSD | | 140 | | °C | Reset, temperature decreasing | 4 |
| IN, BIAS voltage | | -0.3 | | 6.5 | V | | 2 |
| EN, FB, OUT voltage | | -0.3 | | 6 | V | VBIAS + 0.3 V or +6.0 V, whichever is smaller | 2 |
| ESD HBM | | | | 2 | kV | JESD22-A114A | 2 |
| ESD CDM | | | | 500 | V | JESD22-C101B.01 | 2 |
| Junction-to-ambient thermal resistance | θJA | | 136.9 | | °C/W | DGK, 8 pins (TPS74001DGK column) | 3 |
| Junction-to-case (top) thermal resistance | θJCtop | | 35.3 | | °C/W | DGK, 8 pins | 3 |
| Junction-to-board thermal resistance | θJB | | 68 | | °C/W | DGK, 8 pins | 3 |
| Junction-to-top characterization parameter | ψJT | | 0.9 | | °C/W | DGK, 8 pins | 3 |
| Junction-to-board characterization parameter | ψJB | | 67.8 | | °C/W | DGK, 8 pins | 3 |
## CAD (KiCad official)
- Symbol: `TPS74012DGKT`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `tps74012dgkt-etched.step` / `tps74012dgkt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps74012dgkt.step` / `tps74012dgkt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps740) (25 pp, sha256 `ed37adf4d937b6d9`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps74012dgkt-datasheet.pdf)