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Contents

README

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TPS73633DRBR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · VSON-8-EP(3x3)

TPS73633DRBR from Texas Instruments, in a VSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Regulator output voltage at nominal 3.3V; achieves stability without external output capacitor.
2 N/C unconnected No connection; leave unconnected.
3 NR passive Noise reduction bypass pin for fixed voltage version only; connect external capacitor from this pin to ground to filter internal bandgap-generated reference noise and reduce output noise.
4 GND power_in Ground reference; includes exposed thermal pad for heat dissipation; connection to ground plane recommended for optimal thermal performance.
5 EN input Digital enable control input; logic high (≥1.7V) enables regulator output regulation, logic low (≤0.5V) disables to shutdown mode with quiescent current <1μA; TTL/CMOS compatible.
6 N/C unconnected No connection; leave unconnected.
7 N/C unconnected No connection; leave unconnected.
8 IN power_in Input power supply connection; operating voltage range 1.7V to 5.5V; minimum input voltage required is greater of VOUT + VDO (75mV typical at 400mA load) or 1.7V.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSON-8-EP(3x3)
Category Power Management (PMIC)
Pins 9

CAD (KiCad official)

  • Symbol: TPS73633DRBR
  • Footprint: Package_SON:VSON-8-1EP_3x3mm_P0.65mm_EP1.6x2.4mm
  • 3D model: VSON-8-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps73633drbr-etched.step / tps73633drbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps73633drbr.step / tps73633drbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (49 pp, sha256 5ed5c95a399b519d, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF