component
TPS73525DRBR
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), VSON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS73525DRBR
Texas Instruments · Linear Voltage Regulators (LDO) · VSON-8-EP(3x3)
TPS73525DRBR from Texas Instruments, in a VSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; a 2.2-µF ceramic capacitor is required from this pin to ground, and the minimum output capacitance for stability is 2 µF. |
| 2 | NC | unconnected | Not internally connected. |
| 3 | NR | passive | Optional noise-reduction capacitor connection on fixed-voltage versions that bypasses internal band-gap noise; the maximum recommended capacitor is 0.01 µF. |
| 4 | GND | power_in | Ground; the exposed thermal pad must be tied to GND. |
| 5 | EN | input | Driving EN high turns the regulator on and driving it low puts it into shutdown; EN can be connected to IN if not used. |
| 6 | NC | unconnected | Not internally connected. |
| 7 | NC | unconnected | Not internally connected. |
| 8 | IN | power_in | Input supply; a 0.1-µF to 1-µF low-ESR capacitor must be placed from this pin to ground near the device. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSON-8-EP(3x3) |
| Category | Power Management ICs |
| Pins | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO component connections is str | 16 |
CAD (KiCad official)
- Symbol:
TPS73525DRBR - Footprint:
Package_SON:VSON-8-1EP_3x3mm_P0.65mm_EP1.6x2.4mm - 3D model: VSON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps73525drbr-etched.step/tps73525drbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps73525drbr.step/tps73525drbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
90ee834fbba0c989, retrieved 2026-10-28, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).