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TPS73433TDDCRQ1

Public Made by Adom

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps73433tddcrq1factory-2.0.0extractor-text

Verified TPS73433TDDCRQ1

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS73433TDDCRQ1 · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 15-page datasheet
  • ✓distributor: lcsc C2877565, digikey 296-36844-2-ND, mouser 595-TPS73433TDDCRQ1
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-okx0qv4q/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps73433tddcrq1.kicad_sym✓ tps73433tddcrq1.kicad_mod✓ tps73433tddcrq1.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17h ago
viewers tps73433tddcrq1: viewers · Ray 17h ago
package.json Publish 0.1.0 · Ray 17h ago
page.json Set visibility: public · Ray 17h ago
README.md Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1-etched.glb Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1-etched.step tps73433tddcrq1: factory component page (tier=mfr) · Ray 17h ago
tps73433tddcrq1-hero.glb tps73433tddcrq1: hero GLB from the etched model (keeps the MPN mark) · Ray 17h ago
tps73433tddcrq1-hero.overlay.json Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1.glb Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1.kicad_mod Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1.kicad_sym Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1.lbr Publish 0.1.0 · Ray 17h ago
tps73433tddcrq1.step Publish 0.1.0 · Ray 17h ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 17h ago

TPS73433TDDCRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS73433TDDCRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply; the datasheet gives a VIN range of 2.7 V to 6.5 V.
2 GND power_in Ground; the datasheet states the pad must be tied to GND.
3 EN input Driving EN high (VEN(HI) at least 1.2 V) turns on the regulator and driving it low (VEN(LO) at most 0.4 V) puts it into shutdown; EN can be connected to IN if not used.
4 NR passive Fixed-voltage versions only; an external noise reduction capacitor (CNR, for example 0.01μF) on this high-impedance pin bypasses bandgap noise, so a low-leakage capacitor must be used.
5 OUT power_out Regulator output; a ceramic capacitor of at least 2.0μF total typical capacitance is needed from this pin to ground for stability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 2.7 6.5 V 3
Output accuracy (nominal) VOUT -1 1 % Nominal TA = +25°C 3
Output accuracy (load/line/temp) VOUT -2 2 % Over VIN, VOUT + 0.3V ≤ VIN ≤ 6.5V; IOUT, Temp 1mA ≤ IOUT ≤ 250mA 3
Dropout voltage VDO 125 219 mV IOUT = 250mA (VIN = VOUT(NOM), 0.1V) 3
Output current limit ICL 300 580 900 mA VOUT = 0.9 × VOUT(NOM) 3
Ground pin current IGND 45 65 μA 500μA ≤ IOUT ≤ 250mA 3
Shutdown current (IGND) ISHDN 0.15 1 μA VEN ≤ 0.4V 3
Enable high threshold VEN(HI) 1.2 V Enable high (enabled) 3
Enable low threshold VEN(LO) 0 0.4 V Enable low (shutdown) 3
Enable pin current, enabled IEN(HI) 0.03 1 μA VEN = VIN = 6.5V 3
Operating temperature TA -40 105 °C 3
Undervoltage lock-out threshold UVLO 1.9 2.2 2.65 V VIN rising 3
Undervoltage lock-out hysteresis UVLO 70 mV VIN falling 3
Thermal shutdown temperature TSD 165 °C Shutdown, temperature increasing 3
Thermal shutdown reset temperature TSD 145 °C Reset, temperature decreasing 3
Power-supply rejection ratio PSRR 60 dB f = 100Hz; VIN = 3.85V, VOUT = 2.85V, CNR = 0.01μF, IOUT = 100mA 3
Power-supply rejection ratio PSRR 56 dB f = 1kHz; VIN = 3.85V, VOUT = 2.85V, CNR = 0.01μF, IOUT = 100mA 3
Power-supply rejection ratio PSRR 41 dB f = 10kHz; VIN = 3.85V, VOUT = 2.85V, CNR = 0.01μF, IOUT = 100mA 3
Power-supply rejection ratio PSRR 28 dB f = 100kHz; VIN = 3.85V, VOUT = 2.85V, CNR = 0.01μF, IOUT = 100mA 3
Output noise voltage VN 11 x VOUT μVRMS CNR = 0.01μF; BW = 10Hz to 100kHz, VOUT = 2.8V 3
Output noise voltage VN 95 x VOUT μVRMS CNR = none; BW = 10Hz to 100kHz, VOUT = 2.8V 3
Startup time TSTR 45 μs CNR = none; VOUT = 0 ~ 90%, VOUT = 2.85V, RL = 14Ω, COUT = 2.2μF 3
Startup time TSTR 50 μs CNR = 0.01μF; VOUT = 0 ~ 90%, VOUT = 2.85V, RL = 14Ω, COUT = 2.2μF 3
Line regulation ΔVOUT%/ΔVIN 0.02 %/V VOUT(NOM) + 0.3V ≤ VIN ≤ 6.5V 3
Load regulation ΔVOUT%/ΔIOUT 0.005 %/mA 500μA ≤ IOUT ≤ 250mA 3
Input voltage range (absolute maximum) VIN -0.3 7 V 2
Enable pin voltage range (absolute maximum) VEN -0.3 V VIN + 0.3 upper limit as printed 2
Output pin voltage range (absolute maximum) VOUT -0.3 V VIN + 0.3 upper limit as printed 2
Junction temperature range TJ -55 150 °C 2
Storage junction temperature range TSTG -55 150 °C 2
ESD rating, HBM 2 kV 2
ESD rating, CDM 1 kV 2
ESD rating, MM 100 V 2
Junction-to-ambient thermal resistance, low-K board RθJA 280 °C/W Low-K (1s) JEDEC board, DDC package 2
Junction-to-ambient thermal resistance, high-K board RθJA 200 °C/W High-K (2s2p) JEDEC board, DDC package 2
Junction-to-case thermal resistance RθJC 90 °C/W DDC package 2
Output capacitor ESR ESR 1 Ω Maximum ESR of output capacitor 7
Output capacitance COUT 2 2.2 μF Ceramic, total typical capacitance 4

CAD (KiCad official)

  • Symbol: TPS73433TDDCRQ1
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps73433tddcrq1-etched.step / tps73433tddcrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps73433tddcrq1.step / tps73433tddcrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 e5b6bfe2ba4a66e7, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF