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TPS7333QDR

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Texas Instruments Linear Voltage Regulators (LDO), SOIC-8-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS7333QDR

Texas Instruments · Linear Voltage Regulators (LDO) · SOIC-8-150mil

TPS7333QDR from Texas Instruments, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the regulator.
2 EN input Enable input; a logic high shuts down the regulator (sleep mode, 0.5 µA max quiescent current at TJ = 25°C), and the input range is -0.3 V to 11 V.
3 IN power_in Unregulated input supply, absolute maximum -0.3 V to 11 V, tied to pin 4.
4 IN power_in Unregulated input supply, absolute maximum -0.3 V to 11 V, tied to pin 3.
5 OUT power_out Regulated 3.3-V output (3.23 V to 3.37 V), 0 mA to 500 mA output current range, paralleled with pin 6.
6 OUT power_out Regulated 3.3-V output (3.23 V to 3.37 V), 0 mA to 500 mA output current range, paralleled with pin 5.
7 SENSE input Fixed-voltage sense input, normally connected to OUT as close as possible to the device, with absolute maximum -0.3 V to 11 V.
8 RESET output Active-low open-drain NMOS reset output that goes low during an output undervoltage condition and returns high after a 200-ms (typ) delay; absolute maximum -0.3 V to 11 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-150mil
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VI 3.77 10 V TPS7333Q 6
High-level input voltage at EN VIH 2 V 6
Low-level input voltage at EN VIL 0.5 V 6
Output current range IO 0 500 mA 6
Operating virtual junction temperature range TJ -40 125 °C 6
Input voltage range (VI, RESET, SENSE, EN) VI -0.3 11 V 4
Output current IO 2 A 4
Operating virtual junction temperature range TJ -55 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm from case for 10 seconds 4
Continuous power dissipation, D package PD 725 mW TA ≤ 25°C, derate 5.8 mW/°C above 5
Thermal resistance junction-to-ambient, D package RθJA 172 °C/W D package 5
Thermal resistance junction-to-case, D package RθJC 57 °C/W D package 5
Ground current (active mode) 340 400 µA EN ≤ 0.5 V, VI = VO + 1 V, TJ = 25°C 7
Ground current (active mode) 550 µA EN ≤ 0.5 V, VI = VO + 1 V, 0 mA ≤ IO ≤ 500 mA, TJ = -40°C to 125°C 7
Input current (standby mode) 0.01 0.5 µA EN = VI, 2.7 V ≤ VI ≤ 10 V, TJ = 25°C 7
Input current (standby mode) 2 µA EN = VI, 2.7 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 7
Output current limit 1.2 2 A VO = 0 V, VI = 10 V, TJ = 25°C 7
Output current limit 2 A VO = 0 V, VI = 10 V, TJ = -40°C to 125°C 7
Pass-element leakage current in standby mode 0.01 0.5 µA EN = VI, 2.7 V ≤ VI ≤ 10 V, TJ = 25°C 7
Pass-element leakage current in standby mode 1 µA EN = VI, 2.7 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 7
RESET leakage current 0.02 0.5 µA Normal operation, V at RESET = 10 V, TJ = 25°C 7
RESET leakage current 0.5 µA Normal operation, V at RESET = 10 V, TJ = -40°C to 125°C 7
Output voltage temperature coefficient 61 75 ppm/°C TJ = -40°C to 125°C 7
Thermal shutdown junction temperature 165 °C 7
EN logic high (standby mode) 2 V 2.5 V ≤ VI ≤ 6 V, TJ = -40°C to 125°C 7
EN logic high (standby mode) 2.7 V 6 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 7
EN logic low (active mode) 0.5 V 2.7 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 7
EN hysteresis voltage 50 mV TJ = 25°C 7
EN input current -0.5 0.001 0.5 µA 0 V ≤ VI ≤ 10 V, TJ = 25°C 7
EN input current -0.5 0.5 µA 0 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 7
Minimum VI for active pass element 2.05 2.5 V TJ = 25°C 7
Minimum VI for valid RESET 1 1.5 V IO(RESET) = -300 µA, TJ = 25°C 7
Minimum VI for valid RESET 1.9 V IO(RESET) = -300 µA, TJ = -40°C to 125°C 7
Output voltage VO 3.3 V 4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA, TJ = 25°C 11
Output voltage VO 3.23 3.37 V 4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA, TJ = -40°C to 125°C 11
Dropout voltage VDO 4.5 7 mV IO = 10 mA, VI = 3.23 V, TJ = 25°C 11
Dropout voltage VDO 8 mV IO = 10 mA, VI = 3.23 V, TJ = -40°C to 125°C 11
Dropout voltage VDO 44 60 mV IO = 100 mA, VI = 3.23 V, TJ = 25°C 11
Dropout voltage VDO 80 mV IO = 100 mA, VI = 3.23 V, TJ = -40°C to 125°C 11
Dropout voltage VDO 235 300 mV IO = 500 mA, VI = 3.23 V, TJ = 25°C 11
Dropout voltage VDO 400 mV IO = 500 mA, VI = 3.23 V, TJ = -40°C to 125°C 11
Pass-element series resistance 0.44 0.6 Ω (3.23 V, VO)/IO, VI = 3.23 V, IO = 500 mA, TJ = 25°C 11
Pass-element series resistance 0.8 Ω (3.23 V, VO)/IO, VI = 3.23 V, IO = 500 mA, TJ = -40°C to 125°C 11
Input regulation 6 23 mV VI = 4.3 V to 10 V, 50 µA ≤ IO ≤ 500 mA, TJ = 25°C 11
Input regulation 29 mV VI = 4.3 V to 10 V, 50 µA ≤ IO ≤ 500 mA, TJ = -40°C to 125°C 11
Output regulation 21 38 mV IO = 5 mA to 500 mA, 4.3 V ≤ VI ≤ 10 V, TJ = 25°C 11
Output regulation 75 mV IO = 5 mA to 500 mA, 4.3 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 11
Output regulation 31 60 mV IO = 50 µA to 500 mA, 4.3 V ≤ VI ≤ 10 V, TJ = 25°C 11
Output regulation 120 mV IO = 50 µA to 500 mA, 4.3 V ≤ VI ≤ 10 V, TJ = -40°C to 125°C 11
Ripple rejection 43 51 dB IO = 50 µA, f = 120 Hz, TJ = 25°C 11
Ripple rejection 40 dB IO = 50 µA, f = 120 Hz, TJ = -40°C to 125°C 11
Ripple rejection 39 49 dB IO = 500 mA, f = 120 Hz, TJ = 25°C 11
Ripple rejection 36 dB IO = 500 mA, f = 120 Hz, TJ = -40°C to 125°C 11
RESET trip-threshold voltage VIT- 2.868 2.934 3 V VO decreasing, TJ = -40°C to 125°C 1
RESET output low voltage 0.17 0.4 V VI = 2.8 V, IO(RESET) = -1 mA, TJ = 25°C 11
RESET output low voltage 0.4 V VI = 2.8 V, IO(RESET) = -1 mA, TJ = -40°C to 125°C 11
RESET time-out delay 140 200 260 ms See Figure 5, TJ = 25°C 14
RESET time-out delay 100 300 ms See Figure 5, TJ = -40°C to 125°C 14

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper Figure 44 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves adding copper on the PWB to conduct heat away from the device. The RθJA (thermal resistan 33

CAD (KiCad official)

  • Symbol: TPS7333QDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
  • 3D model files: tps7333qdr-etched.step / tps7333qdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7333qdr.step / tps7333qdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 76a79e006bd9311d, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF