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TPS7325QD
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS7325QD
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
TPS7325QD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for the regulator; all voltages are specified with respect to this terminal. |
| 2 | EN | input | Active-low enable: a logic high shuts down the regulator into sleep mode (0.5 µA max quiescent at TJ = 25°C), and the pin is rated -0.3 V to 11 V. |
| 3 | IN | power_in | Unregulated input supply, rated -0.3 V to 11 V; pins 3 and 4 are both IN. |
| 4 | IN | power_in | Unregulated input supply, rated -0.3 V to 11 V; pins 3 and 4 are both IN. |
| 5 | OUT | power_out | Regulated output (2.5 V fixed for TPS7325, 0 to 500 mA output current range); pins 5 and 6 are both OUT. |
| 6 | OUT | power_out | Regulated output (2.5 V fixed for TPS7325, 0 to 500 mA output current range); pins 5 and 6 are both OUT. |
| 7 | SENSE | input | Output-voltage sense input for the fixed-voltage TPS7325 (FB on the adjustable TPS7301), which should be tied to OUT as close to the device as possible and is rated -0.3 V to 11 V. |
| 8 | RESET | output | Open-drain NMOS active-low reset output that goes low on output undervoltage and returns high after a 200-ms (typ) delay once the condition ends. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS7325QD - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps7325qd-etched.step/tps7325qd-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7325qd.step/tps7325qd.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (46 pp, sha256
64058afafde102b9, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS7325QD
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
TPS7325QD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for the regulator; all voltages are specified with respect to this terminal. |
| 2 | EN | input | Active-low enable: a logic high shuts down the regulator into sleep mode (0.5 µA max quiescent at TJ = 25°C), and the pin is rated -0.3 V to 11 V. |
| 3 | IN | power_in | Unregulated input supply, rated -0.3 V to 11 V; pins 3 and 4 are both IN. |
| 4 | IN | power_in | Unregulated input supply, rated -0.3 V to 11 V; pins 3 and 4 are both IN. |
| 5 | OUT | power_out | Regulated output (2.5 V fixed for TPS7325, 0 to 500 mA output current range); pins 5 and 6 are both OUT. |
| 6 | OUT | power_out | Regulated output (2.5 V fixed for TPS7325, 0 to 500 mA output current range); pins 5 and 6 are both OUT. |
| 7 | SENSE | input | Output-voltage sense input for the fixed-voltage TPS7325 (FB on the adjustable TPS7301), which should be tied to OUT as close to the device as possible and is rated -0.3 V to 11 V. |
| 8 | RESET | output | Open-drain NMOS active-low reset output that goes low on output undervoltage and returns high after a 200-ms (typ) delay once the condition ends. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `TPS7325QD`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tps7325qd-etched.step` / `tps7325qd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps7325qd.step` / `tps7325qd.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps73) (46 pp, sha256 `64058afafde102b9`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps7325qd-datasheet.pdf)