component
TPS73218MDBVREP
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| tps73218mdbvrep-etched.step | 23d ago |
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TPS73218MDBVREP
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS73218MDBVREP from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Unregulated input supply, with VIN specified from 1.7 V to 5.5 V and an absolute maximum of -0.3 V to 6 V. |
| 2 | GND | power_in | Ground pin; the datasheet recommends separate ground planes for VIN and VOUT, each connected only to the GND pin, with bypass capacitor grounds tied directly to GND. |
| 3 | EN | input | Active-high enable compatible with TTL-CMOS levels; driving it below 0.5 V (max) shuts the regulator off and reduces ground current to about 10 nA, with an absolute maximum of -0.3 V to 6 V, and it can be tied to IN if shutdown is not needed. |
| 4 | NR/FB | passive | Pin 4 is shared: for the fixed-voltage versions, including the TPS73218, it is NR, where an external capacitor to GND filters the internal reference noise, while FB is used only on the adjustable TPS73201. |
| 5 | OUT | power_out | Regulator output, which is stable without an output capacitor; fixed versions range from 1.2 V to 5 V, and absolute maximum VOUT is -0.3 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 1.7 | 5.5 | V | 5 | ||
| Output voltage accuracy (line, load and temperature) | -1 | 0.5 | 1 | % | VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 250mA | 5 | |
| Initial output voltage accuracy | -0.5 | 0.5 | % | TA = 25°C (nominal) | 5 | ||
| Dropout voltage | VDO | 40 | 150 | mV | VIN = VOUT(nom) – 0.1V, IOUT = 250mA | 5 | |
| Output current limit | ICL | 250 | 425 | 600 | mA | VOUT = 0.9 × VOUT(nom) | 5 |
| Reverse leakage current (–IIN) | IREV | 0.1 | 15 | µA | VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT | 5 | |
| Ground pin current | IGND | 400 | 550 | µA | IOUT = 10mA (IQ) | 5 | |
| Ground pin current | IGND | 650 | 950 | µA | IOUT = 250mA | 5 | |
| Shutdown current (IGND) | ISHDN | 0.02 | 1 | µA | VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V | 5 | |
| Enable pin high-level input voltage (enabled) | VEN(HI) | 1.7 | V | 5 | |||
| Enable pin low-level input voltage (shutdown) | VEN(LO) | 0 | 0.5 | V | 5 | ||
| Enable pin current (enabled) | IEN(HI) | 0.02 | 0.1 | µA | VEN = 5.5V | 5 | |
| Thermal shutdown temperature | TSD | 160 | °C | Shutdown, temperature rising | 5 | ||
| Thermal shutdown reset temperature | TSD | 140 | °C | Reset, temperature falling | 5 | ||
| Operating ambient temperature | TA | -55 | 125 | °C | 5 | ||
| Input voltage (absolute maximum) | VIN | -0.3 | 6 | V | Measured at operating junction temperature range | 4 | |
| Enable voltage (absolute maximum) | VEN | -0.3 | 6 | V | Measured at operating junction temperature range | 4 | |
| Output voltage (absolute maximum) | VOUT | -0.3 | 5.5 | V | Measured at operating junction temperature range | 4 | |
| Ambient temperature range (absolute maximum) | TA | -55 | 150 | °C | 4 | ||
| Storage temperature range | -65 | 150 | °C | 4 | |||
| ESD rating, HBM | 2 | kV | 4 | ||||
| ESD rating, CDM | 500 | V | 4 | ||||
| Junction-to-ambient thermal resistance (RθJA) | RθJA | 255 | °C/W | DBV package, low-K JEDEC board (1s) | 4 | ||
| Junction-to-ambient thermal resistance (RθJA) | RθJA | 180 | °C/W | DBV package, high-K JEDEC board (2s2p) | 4 | ||
| Junction-to-case thermal resistance (RθJC) | RθJC | 64 | °C/W | DBV package | 4 |
CAD (KiCad official)
- Symbol:
TPS73218MDBVREP - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps73218mdbvrep-etched.step/tps73218mdbvrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps73218mdbvrep.step/tps73218mdbvrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
bad03516f0a9f6f4, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).