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TPS73115DBVR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps73115dbvrfactory-2.0.0extractor-text

Verified TPS73115DBVR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS73115DBVR · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C2870497, digikey 296-41769-2-ND, mouser 595-TPS73115DBVR
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ufj9qqer/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps73115dbvr.kicad_sym✓ tps73115dbvr.kicad_mod✓ tps73115dbvr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers tps73115dbvr: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
tps73115dbvr-etched.glb Publish 0.1.0 · Ray 1d ago
tps73115dbvr-etched.step tps73115dbvr: factory component page (tier=mfr) · Ray 1d ago
tps73115dbvr-hero.glb tps73115dbvr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
tps73115dbvr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
tps73115dbvr.glb Publish 0.1.0 · Ray 1d ago
tps73115dbvr.kicad_mod Publish 0.1.0 · Ray 1d ago
tps73115dbvr.kicad_sym Publish 0.1.0 · Ray 1d ago
tps73115dbvr.lbr Publish 0.1.0 · Ray 1d ago
tps73115dbvr.step Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 5 pins · Ray 1d ago

TPS73115DBVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS73115DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN input Input supply for the regulator, with a recommended input voltage range of 1.7 V to 5.5 V.
2 GND power_in Ground pin for the regulator.
3 EN input Driving EN high turns on the regulator and driving it low puts it into shutdown mode; EN can be connected to IN if not used.
4 NR/FB input On fixed-voltage versions, an external capacitor on NR bypasses internal bandgap noise to very low output noise levels.
5 OUT output Regulator output, which has no output capacitor requirements for stability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 1.7 5.5 V 5
Output voltage accuracy, nominal -0.5 0.5 % TJ = 25°C 5
Output voltage accuracy over line, load and temperature -1 0.5 1 % VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 150mA 5
Dropout voltage VDO 30 100 mV IOUT = 150mA (VIN = VOUT(NOM) - 0.1V) 5
Output current limit ICL 150 360 500 mA VOUT = 0.9 × VOUT(nom) 5
Reverse leakage current IREV 0.1 10 µA VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT 5
Ground pin current, legacy silicon IGND 400 550 µA IOUT = 10mA (IQ), legacy silicon 5
Ground pin current, new silicon IGND 400 630 µA IOUT = 10mA (IQ), new silicon 5
Ground pin current at full load IGND 550 750 µA IOUT = 150mA 5
Shutdown current, legacy silicon ISHDN 0.02 1 µA VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V, -40°C ≤ TJ ≤ 100℃, legacy silicon 5
Shutdown current, new silicon ISHDN 0.02 1 µA VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5V, new silicon 5
Enable pin current (enabled) IEN(high) 0.02 0.1 µA VEN = 5.5V 5
EN pin low (shutdown) VEN(low) 0 0.5 V 5
EN pin high (enabled) VEN(high) 1.7 V Maximum printed as VIN 5
Power-supply rejection ratio PSRR 58 dB f = 100Hz, IOUT = 150mA 5
Power-supply rejection ratio PSRR 37 dB f = 10kHz, IOUT = 150mA 5
Line regulation ΔVOUT(ΔVIN) 0.01 %/V VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V 5
Load regulation ΔVOUT(ΔIOUT) 0.002 %/mA 1mA ≤ IOUT ≤ 150mA 5
Load regulation ΔVOUT(ΔIOUT) 0.0005 %/mA 10mA ≤ IOUT ≤ 150mA 5
Output impedance in dropout ZO(DO) 0.25 Ω 1.7V ≤ VIN ≤ VOUT + VDO 5
Short-circuit current ISC 200 mA VOUT = 0V 5
Startup time tSTR 600 µs VOUT = 3V, RL = 30Ω, COUT = 1μF, CNR = 0.01μF 5
Thermal shutdown temperature, shutdown TSD 160 °C Shutdown, temperature increasing 5
Thermal shutdown temperature, reset TSD 140 °C Reset, temperature decreasing 5
Input supply voltage VIN 1.7 5.5 V 4
Output current IOUT 0 150 mA 4
Operating junction temperature TJ -40 125 °C 4
Input voltage VIN -0.3 6 V 4
Enable voltage VEN -0.3 6 V 4
Output voltage VOUT -0.3 5.5 V 4
Noise reduction and feedback pin voltage VNR, VFB -0.3 6 V 4
Operating junction temperature TJ -55 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance, new silicon RθJA 185.2 °C/W 4
Junction-to-ambient thermal resistance, legacy silicon RθJA 207.2 °C/W 4
Junction-to-case (top) thermal resistance, new silicon RθJC(top) 82.9 °C/W 4
Junction-to-case (top) thermal resistance, legacy silicon RθJC(top) 124.2 °C/W 4
Junction-to-board thermal resistance, new silicon RθJB 53.1 °C/W 4
Junction-to-board thermal resistance, legacy silicon RθJB 35 °C/W 4
Junction-to-top characterization parameter, new silicon ψJT 21.1 °C/W 4
Junction-to-top characterization parameter, legacy silicon ψJT 13.5 °C/W 4
Junction-to-board characterization parameter, new silicon ψJB 52.7 °C/W 4
Junction-to-board characterization parameter, legacy silicon ψJB 34.1 °C/W 4

CAD (KiCad official)

  • Symbol: TPS73115DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps73115dbvr-etched.step / tps73115dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps73115dbvr.step / tps73115dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 f38aede3fd278b3a, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF