# TPS73047DBVR

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS73047DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Device input pin that supplies the regulator; the pin table gives only this function, and the input voltage range is specified in the recommended operating conditions. |
| 2 | GND | power_in | Regulator ground reference pin for the device. |
| 3 | EN | input | Active-high enable: driving EN high turns the regulator on and driving it low puts it in shutdown mode; if shutdown is not needed, EN should be tied to IN. |
| 4 | NC/NR | passive | On the old chip this is the noise-reduction pin, where an external capacitor filters bandgap noise; on the new chip it is not internally connected and may be tied to GND to improve thermal performance or left floating. |
| 5 | OUT | power_out | Regulator output pin that delivers the regulated output voltage to the load. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN (recommended operating) | VIN | 2.7 |  | 5.5 | V |  | 4 |
| Enable voltage (recommended operating) | VEN | 0 |  | 5.5 | V |  | 4 |
| Output current (recommended operating) | IOUT | 0 |  | 200 | mA |  | 4 |
| Operating junction temperature (recommended) | TJ | -40 |  | 125 | °C |  | 4 |
| Output capacitor COUT | COUT | 2.2 |  | 10 | µF | Min 4.7 µF if CFF not used or VOUT(nom) < 1.8V; new chip min effective 0.47 µF (notes 1, 2) | 4 |
| Input capacitor CIN (old chip) | CIN | 0.1 |  | 1 | µF |  | 4 |
| Noise-reduction capacitor CNR (old chip only) | CNR | 0 |  | 10 | nF |  | 4 |
| Feedforward capacitor CFF (new chip) | CFF | 0 | 10 | 100 | nF |  | 4 |
| Input, enable and output voltage (old chip) | VIN, VEN, VOUT | -0.3 |  | 6 | V |  | 4 |
| Input and enable voltage (new chip) | VIN, VEN | -0.3 |  | 6.5 | V |  | 4 |
| Output voltage (new chip) | VOUT | -0.3 |  |  | V | Max printed as VIN + 0.3 (or 6.5 V, whichever is smaller) | 4 |
| Operating junction temperature (DBV package) | TJ | -40 |  | 150 | °C | DBV package | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001, all pins | 4 |
| ESD CDM | V(ESD) | -500 |  | 500 | V | CDM per JEDEC JESD22-C101, all pins | 4 |
| Input voltage range | VIN | 2.7 |  | 5.5 | V |  | 5 |
| Continuous output current | IOUT | 0 |  | 200 | mA |  | 5 |
| Output voltage accuracy |  | -2 |  | 2 | % | 0µA < IOUT < 200mA, VOUT+1V < VIN < 5.5V | 5 |
| Dropout voltage | VDO |  | 120 | 210 | mV | VIN= VOUT - 0.1V, IOUT = 200mA | 5 |
| Output current limit (old chip) | ICL | 285 |  | 600 | mA | VOUT = 0V (old chip) | 5 |
| Output current limit (new chip) | ICL | 320 |  | 460 | mA | IN = VOUT(NOM) + 1V, VOUT = 0.9 x VOUT(NOM) (new chip only) | 5 |
| Quiescent (GND) current (old chip) | IGND |  | 170 | 220 | µA | 0µA ≤ IO ≤ 200mA (old chip) | 5 |
| Quiescent (GND) current (new chip) | IGND |  | 250 | 1000 | µA | 0µA ≤ IO ≤ 200mA (new chip) | 5 |
| Shutdown current (old chip) | ISHDN |  | 0.07 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (old chip) | 5 |
| Shutdown current (new chip) | ISHDN |  | 0.01 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (new chip) | 5 |
| High-level enable input voltage (old chip) | VEN(HI) | 1.7 |  |  | V | 2.7V ≤ VIN ≤ 5.5V | 6 |
| Low-level enable input voltage (old chip) | VEN(LOW) | 0 |  | 0.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 |
| Low-level enable input voltage (new chip) | VEN(LOW) | 0 |  | 0.425 | V | 2.7V ≤ VIN ≤ 5.5V (new chip) | 6 |
| Enable pin current | IEN | -1 |  | 1 | µA | VEN = 0V | 6 |
| UVLO threshold, VIN rising (old chip) | VUVLO | 2.25 |  | 2.65 | V | VIN rising (old chip) | 6 |
| UVLO threshold, VIN rising (new chip) | VUVLO | 1.32 |  | 1.6 | V | VIN rising (new chip) | 6 |
| Junction-to-ambient thermal resistance (DBV SOT-23-5, new chip) | RθJA |  | 182.3 |  | °C/W |  | 5 |
| Junction-to-case (top) thermal resistance (DBV SOT-23-5, new chip) | RθJC(top) |  | 114.8 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance (DBV SOT-23-5, new chip) | RθJB |  | 79.1 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter (DBV SOT-23-5, new chip) | ψJT |  | 56.8 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter (DBV SOT-23-5, new chip) | ψJB |  | 78.8 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `TPS73047DBVR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps73047dbvr-etched.step` / `tps73047dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps73047dbvr.step` / `tps73047dbvr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps730) (42 pp, sha256 `14439297a4ab9a2b`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps73047dbvr-datasheet.pdf)