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TPS73033DBVT
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS73033DBVT
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS73033DBVT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | Input to the device; the recommended input voltage range is 2.7 V to 5.5 V. |
| 2 | GND | power_in | Regulator ground. |
| 3 | EN | input | Enable pin: driving EN high turns on the regulator and driving it low puts the regulator into shutdown mode; EN can be connected to IN if not used. |
| 4 | NC/NR | passive | Noise-reduction pin on the legacy chip, where an external capacitor (CNR 0 to 10 nF) filters band-gap noise; on the new chip this is a no-connect pin that is not internally connected and may be tied to GND or left floating. |
| 5 | OUT | output | Output of the regulator, which requires a minimum COUT of 2.2 µF for stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 2.7 | 5.5 | V | 4 | ||
| Enable voltage | VEN | 0 | 5.5 | V | 4 | ||
| Output current | IOUT | 0 | 200 | mA | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Output capacitor | COUT | 2.2 | 10 | µF | footnotes (1),(2): minimum 4.7 µF if CFF not used or VOUT(nom) < 1.8 V; minimum effective 0.47 µF for new chip | 4 | |
| Input capacitor | CIN | 0.1 | µF | legacy chip | 4 | ||
| Input capacitor | CIN | 1 | µF | new chip | 4 | ||
| Noise reduction capacitor | CNR | 0 | 10 | nF | legacy chip only | 4 | |
| Feed-forward capacitor | CFF | 0 | 10 | 100 | nF | new chip; optional | 4 |
| Absolute maximum voltage VIN, VEN, VOUT | VIN, VEN, VOUT | -0.3 | 6 | V | legacy chip | 4 | |
| Absolute maximum voltage VIN, VEN | VIN, VEN | -0.3 | 6.5 | V | new chip | 4 | |
| Absolute maximum voltage VOUT | VOUT | -0.3 | V | new chip; maximum is VIN + 0.3 V or 6.5 V, whichever is smaller | 4 | ||
| Operating junction temperature (DBV package) | TJ | -40 | 150 | °C | DBV package | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Output voltage accuracy | VOUT | -2 | 2 | % | 0µA < IOUT < 200mA, VOUT+ 1V < VIN < 5.5V | 5 | |
| Output current limit | ICL | 285 | 600 | mA | VOUT = 0V (legacy chip) | 5 | |
| Output current limit | ICL | 320 | 460 | mA | VIN = VOUT(NOM) + 1 V, VOUT = 0.9 x VOUT(NOM) (new chip only) | 5 | |
| Quiescent current (GND current) | IGND | 170 | 220 | µA | 0µA ≤ IO ≤ 200mA (legacy chip) | 5 | |
| Quiescent current (GND current) | IGND | 250 | 1000 | µA | 0µA ≤ IO ≤ 200mA (new chip) | 5 | |
| Enable pin current | IEN | -1 | 1 | µA | VEN = 0 V | 6 | |
| UVLO threshold | VUVLO | 2.25 | 2.65 | V | VIN rising (legacy chip) | 6 | |
| UVLO threshold | VUVLO | 1.32 | 1.6 | V | VIN rising (new chip) | 6 | |
| High-level enable input voltage | VEN(HI) | 1.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | ||
| High-level enable input voltage | VEN(HI) | 0.85 | V | 2.7V ≤ VIN ≤ 5.5V (new chip) | 6 | ||
| Low-level enable input voltage | VEN(LOW) | 0 | 0.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | |
| Low-level enable input voltage | VEN(LOW) | 0 | 0.425 | V | 2.7V ≤ VIN ≤ 5.5V (new chip) | 6 | |
| Dropout voltage | VDO | 120 | 210 | mV | VIN= VOUT - 0.1V, IOUT = 200mA | 5 | |
| Line regulation | ΔVOUT/ΔVIN | 0.05 | %/V | VOUT + 1V ≤ VIN ≤ 5.5V | 5 | ||
| Load regulation | ΔVOUT/ΔIOUT | 5 | mV | 0µA ≤ IOUT ≤ 200mA | 5 | ||
| Short-circuit current limit | ISC | 175 | mA | VOUT = 0V (new chip) | 5 | ||
| Shutdown current | ISHDN | 0.07 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (legacy chip) | 5 | |
| Shutdown current | ISHDN | 0.01 | 1 | µA | VEN = 0V, 2.7V < VIN < 5.5V (new chip) | 5 | |
| Power-supply rejection ratio | PSRR | 70 | dB | f = 100Hz, IOUT = 10mA (legacy chip) | 6 | ||
| Power-supply rejection ratio | PSRR | 64 | dB | f = 100Hz, IOUT = 10mA (new chip) | 6 | ||
| Power-supply rejection ratio | PSRR | 68 | dB | f = 100Hz, IOUT = 200mA (legacy chip) | 6 | ||
| Power-supply rejection ratio | PSRR | 65 | dB | f = 100Hz, IOUT = 200mA (new chip) | 6 | ||
| Power-supply rejection ratio | PSRR | 49 | dB | f = 10kHz, IOUT = 200mA (new chip) | 6 | ||
| Power-supply rejection ratio | PSRR | 43 | dB | f = 100kHz, IOUT = 200mA (legacy chip) | 6 | ||
| Power-supply rejection ratio | PSRR | 39 | dB | f = 100kHz, IOUT = 200mA (new chip) | 6 | ||
| Output noise voltage | Vn | 33 | µVRMS | BW = 200Hz to 100kHz, IOUT = 200mA, CNR = 0.01µF (legacy chip) | 6 | ||
| Output noise voltage | Vn | 69 | µVRMS | BW = 200Hz to 100kHz, IOUT = 200mA (new chip) | 6 | ||
| Undervoltage lockout hysteresis | VUVLO(HYST) | 100 | mV | VCC rising (legacy chip) | 6 | ||
| Undervoltage lockout hysteresis | VUVLO(HYST) | 130 | mV | VCC rising (new chip) | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 182.3 | °C/W | DBV (SOT23-5), new chip | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 114.8 | °C/W | DBV (SOT23-5), new chip | 5 | ||
| Junction-to-board thermal resistance | RθJB | 79.1 | °C/W | DBV (SOT23-5), new chip | 5 | ||
| Junction-to-top characterization parameter | ψJT | 56.8 | °C/W | DBV (SOT23-5), new chip | 5 | ||
| Junction-to-board characterization parameter | ψJB | 78.8 | °C/W | DBV (SOT23-5), new chip | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material. NanoStar is a trademark of Texas Instruments. | 28 |
CAD (KiCad official)
- Symbol:
TPS73033DBVT - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps73033dbvt-etched.step/tps73033dbvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps73033dbvt.step/tps73033dbvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
ba08deb68c80cc87, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).