component
TPS73033DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS73033DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS73033DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply voltage, 2.7V to 5.5V range required for stable operation above output voltage plus dropout voltage. |
| 2 | GND | power_in | Regulator ground reference. |
| 3 | EN | input | Enable control input; logic high enables regulator, logic low puts device in shutdown mode; if unused, connect to IN. |
| 4 | NC/NR | unconnected | No-connect pin (new chip) or noise reduction pin (old chip) with external capacitor for filtering internal bandgap reference noise. |
| 5 | OUT | power_out | Regulated output at 3.3V nominal with 200mA maximum continuous output current; typical dropout voltage 120mV at full current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range (recommended) | VIN | 2.7 | 5.5 | V | 4 | ||
| Enable voltage (recommended) | VEN | 0 | 5.5 | V | 4 | ||
| Continuous output current (recommended) | IOUT | 0 | 200 | mA | 4 | ||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | 4 | ||
| Input voltage range | VIN | 2.7 | 5.5 | V | 5 | ||
| Continuous output current | IOUT | 0 | 200 | mA | 5 | ||
| Output voltage accuracy | VOUT | -2 | 2 | % | 0µA < IOUT < 200mA, VOUT+1V < VIN < 5.5V | 5 | |
| Dropout voltage | VDO | 120 | 210 | mV | VIN= VOUT - 0.1V, IOUT = 200mA | 5 | |
| Output current limit (old chip) | ICL | 285 | 600 | mA | VOUT = 0V (old chip) | 5 | |
| Output current limit (new chip) | ICL | 320 | 460 | mA | VIN = VOUT(NOM) + 1V, VOUT = 0.9 x VOUT(NOM) (new chip only) | 5 | |
| Quiescent (GND) current (old chip) | IGND | 170 | 220 | µA | 0µA ≤ IO ≤ 200mA (old chip) | 5 | |
| Quiescent (GND) current (new chip) | IGND | 250 | 1000 | µA | 0µA ≤ IO ≤ 200mA (new chip) | 5 | |
| Shutdown current (old chip) | ISHDN | 0.07 | 1 | µA | VEN = 0V, 2.7V < VI < 5.5V (old chip) | 5 | |
| Shutdown current (new chip) | ISHDN | 0.01 | 1 | µA | VEN = 0V, 2.7V < VI < 5.5V (new chip) | 5 | |
| High-level enable input voltage (old chip) | VEN(HI) | 1.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | ||
| Low-level enable input voltage (old chip) | VEN(LOW) | 0 | 0.7 | V | 2.7V ≤ VIN ≤ 5.5V | 6 | |
| Low-level enable input voltage (new chip) | VEN(LOW) | 0 | 0.425 | V | 2.7V ≤ VIN ≤ 5.5V (new chip) | 6 | |
| Enable pin current | IEN | -1 | 1 | µA | VEN = 0V | 6 | |
| UVLO threshold, VIN rising (old chip) | VUVLO | 2.25 | 2.65 | V | VIN rising (old chip) | 6 | |
| UVLO threshold, VIN rising (new chip) | VUVLO | 1.32 | 1.6 | V | VIN rising (new chip) | 6 | |
| Input/enable/output voltage (old chip) | VIN, VEN, VOUT | -0.3 | 6 | V | old chip | 4 | |
| Input/enable voltage (new chip) | VIN, VEN | -0.3 | 6.5 | V | new chip | 4 | |
| Output voltage (new chip) | VOUT | -0.3 | V | new chip; max printed as VIN + 0.3, limited to 6.5 V | 4 | ||
| Operating junction temperature (DBV package) | TJ | -40 | 150 | °C | DBV package | 4 | |
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input capacitor (old chip) | CIN | 0.1 | 1 | µF | old chip | 4 | |
| Output capacitor | COUT | 2.2 | 10 | µF | 4 | ||
| Noise reduction capacitor (old chip only) | CNR | 0 | 10 | nF | old chip only | 4 | |
| Feedforward capacitor (new chip, optional) | CFF | 0 | 10 | 100 | nF | new chip, optional | 4 |
| Line regulation | ΔVOUT/ΔVIN | 0.05 | %/V | VOUT + 1V ≤ VIN ≤ 5.5V | 5 | ||
| Load regulation | ΔVOUT/ΔIOUT | 5 | mV | 0µA ≤ IOUT ≤ 200mA | 5 | ||
| Short-circuit current limit (new chip) | ISC | 175 | mA | VOUT = 0V (new chip) | 5 | ||
| UVLO hysteresis (old chip) | VUVLO(HYST) | 100 | mV | VCC rising (old chip) | 6 | ||
| UVLO hysteresis (new chip) | VUVLO(HYST) | 130 | mV | VCC rising (new chip) | 6 | ||
| Power supply rejection ratio | PSRR | 70 | dB | f = 100Hz, IOUT = 10mA (old chip) | 6 | ||
| Power supply rejection ratio | PSRR | 64 | dB | f = 100Hz, IOUT = 10mA (new chip) | 6 | ||
| Power supply rejection ratio | PSRR | 68 | dB | f = 100Hz, IOUT = 200mA (old chip) | 6 | ||
| Power supply rejection ratio | PSRR | 65 | dB | f = 100Hz, IOUT = 200mA (new chip) | 6 | ||
| Power supply rejection ratio | PSRR | 49 | dB | f = 10kHz, IOUT = 200mA (new chip) | 6 | ||
| Power supply rejection ratio | PSRR | 43 | dB | f = 100kHz, IOUT = 200mA (old chip) | 6 | ||
| Power supply rejection ratio | PSRR | 39 | dB | f = 100kHz, IOUT = 200mA (new chip) | 6 | ||
| Output noise voltage (old chip) | Vn | 33 | µVRMS | BW = 200Hz to 100kHz, IOUT = 200mA, CNR = 0.01µF | 6 | ||
| Output noise voltage (new chip) | Vn | 69 | µVRMS | BW = 200Hz to 100kHz, IOUT = 200mA (new chip) | 6 | ||
| Startup time (old chip) | tSTR | 50 | µs | RL = 14Ω, COUT = 1µF, CNR = 0.001µF | 6 | ||
| Startup time (new chip) | tSTR | 500 | µs | RL = 14Ω, COUT = 1µF, CNR = 0.01µF (new chip) | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 182.3 | °C/W | DBV (SOT-23-5), new chip | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 114.8 | °C/W | DBV (SOT-23-5), new chip | 5 | ||
| Junction-to-board thermal resistance | RθJB | 79.1 | °C/W | DBV (SOT-23-5), new chip | 5 | ||
| Junction-to-top characterization parameter | ψJT | 56.8 | °C/W | DBV (SOT-23-5), new chip | 5 | ||
| Junction-to-board characterization parameter | ψJB | 78.8 | °C/W | DBV (SOT-23-5), new chip | 5 |
CAD (KiCad official)
- Symbol:
TPS73033DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps73033dbvr-etched.step/tps73033dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps73033dbvr.step/tps73033dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (42 pp, sha256
14439297a4ab9a2b, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).