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Initial commit: component/tps73001dbvr

Ray ·d622df9e3a ·1d ago
2 files changed +231
README.mdadded+43
@@ -0,0 +1,43 @@+# TPS73001DBVR++**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-6++TPS73001DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IN | power_in | Regulator input supply; recommended VIN is 2.7 V to 5.5 V, and a ceramic bypass capacitor of at least 0.1 µF (old chip) or 1 µF (new chip) must be placed close to IN and GND. |+| 2 | GND | power_in | Regulator ground; connect input and output capacitor ground returns directly to this pin to maximize PSRR and noise performance. |+| 3 | EN | input | Active-high enable; drive above VEN(HI) to turn the regulator on and below VEN(LOW) to shut it down, must not be left floating, and may be tied to IN if shutdown is not needed. |+| 4 | NC/NR | passive | On the old chip this is the noise reduction pin, where an external capacitor of at most 0.1 µF (typically 0.01 µF) filters bandgap noise and must not be loaded resistively or inductively; on the new chip it is not internally connected and may be left floating or tied to GND. |+| 5 | FB | input | Feedback input of the adjustable version that sets VOUT through an external R1/R2 divider referenced to a 1.225 V typical internal reference; this pin does not exist on the fixed-voltage DBV versions. |+| 6 | OUT | power_out | Regulator output, which requires a ceramic output capacitor of at least 2.2 µF to GND (4.7 µF when VOUT is below 1.8 V or no feedforward capacitor is used) for stability. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOT-23-6 |+| Category | Power Management (PMIC) |+| Pins | 6 |++## CAD (KiCad official)++- Symbol: `TPS73001DBVR`+- Footprint: `Package_TO_SOT_SMD:SOT-23-6`+- 3D model: SOT-23-6 (KiCad packages3D, STEP)+- 3D model files: `tps73001dbvr-etched.step` / `tps73001dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps73001dbvr.step` / `tps73001dbvr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps730) (42 pp, sha256 `14439297a4ab9a2b`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps73001dbvr-datasheet.pdf)
page.jsonadded+188
@@ -0,0 +1,188 @@+{+  "slug": "tps73001dbvr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "tps73001dbvr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tps73001dbvr.kicad_sym",+    "tps73001dbvr.kicad_mod",+    "tps73001dbvr.glb",+    "tps73001dbvr.step",+    "tps73001dbvr.lbr",+    "docs/hero.png",+    "docs/tps73001dbvr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "tps73001dbvr-hero.glb",+    "tps73001dbvr-hero.overlay.json"+  ],+  "component": {+    "mpn": "TPS73001DBVR",+    "manufacturer": "Texas Instruments",+    "package": "SOT-23-6",+    "pin_count": 6,+    "category": "Power Management (PMIC)",+    "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+    "datasheet": "https://www.ti.com/cn/lit/gpn/tps730",+    "parts": {+      "symbol": "tps73001dbvr.kicad_sym",+      "footprint": "tps73001dbvr.kicad_mod",+      "model_3d": "tps73001dbvr-hero.glb",+      "model_3d_plain": "tps73001dbvr.glb",+      "model_3d_step": "tps73001dbvr-etched.step",+      "model_3d_step_plain": "tps73001dbvr.step",+      "lbr": "tps73001dbvr.lbr"+    },+    "distributor_links": {+      "lcsc": "C132054",+      "digikey": "296-27055-2-ND",+      "mouser": "595-TPS73001DBVR"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T01:05:27Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-27055-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-TPS73001DBVR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "IN",+        "type": "power_in",+        "description": "Regulator input supply; recommended VIN is 2.7 V to 5.5 V, and a ceramic bypass capacitor of at least 0.1 µF (old chip) or 1 µF (new chip) must be placed close to IN and GND."+      },+      {+        "number": "2",+        "name": "GND",+        "type": "power_in",+        "description": "Regulator ground; connect input and output capacitor ground returns directly to this pin to maximize PSRR and noise performance."+      },+      {+        "number": "3",+        "name": "EN",+        "type": "input",+        "description": "Active-high enable; drive above VEN(HI) to turn the regulator on and below VEN(LOW) to shut it down, must not be left floating, and may be tied to IN if shutdown is not needed."+      },+      {+        "number": "4",+        "name": "NC/NR",+        "type": "passive",+        "description": "On the old chip this is the noise reduction pin, where an external capacitor of at most 0.1 µF (typically 0.01 µF) filters bandgap noise and must not be loaded resistively or inductively; on the new chip it is not internally connected and may be left floating or tied to GND."+      },+      {+        "number": "5",+        "name": "FB",+        "type": "input",+        "description": "Feedback input of the adjustable version that sets VOUT through an external R1/R2 divider referenced to a 1.225 V typical internal reference; this pin does not exist on the fixed-voltage DBV versions."+      },+      {+        "number": "6",+        "name": "OUT",+        "type": "power_out",+        "description": "Regulator output, which requires a ceramic output capacitor of at least 2.2 µF to GND (4.7 µF when VOUT is below 1.8 V or no feedforward capacitor is used) for stability."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The datasheet covers both old and new silicon (chip revisions). Pin 4 is labelled NC/NR: it is a noi; The datasheet pin table lists IN as type 'I' (input). It was mapped to KiCad power_in because it is ; The datasheet pin table lists OUT as type 'O'. It was mapped to KiCad power_out for a regulator outp"+        ],+        "pages_sent": 24,+        "cost_usd": 0.1246,+        "at": "2026-10-08T01:05:11"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/tps730",+        "pages": 42,+        "sha256": "14439297a4ab9a2b",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 6,+        "described": 6,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "tps73001dbvr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          2.8,+          2.9,+          1.55+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "c9fe686b4d1b56927a41fa84a9bc1efb61d8a45a123a3db43bcaa05c2891d635",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "tps73001dbvr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          2.8,+          2.9,+          1.55+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "0e345cd676cc744d9c4c5bf7941ff38e88f31445c024033fd42d2f3f4e60d9ea",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file