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TPS72730DSET
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6(1.5x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS72730DSET
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6(1.5x1.5)
TPS72730DSET from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output voltage pin; a small 1-μF ceramic capacitor is needed from this pin to ground to assure stability. |
| 2 | NC | unconnected | No connection; this pin can be tied to ground to improve thermal dissipation. |
| 3 | GND | power_in | Ground pin. |
| 4 | EN | input | Driving EN over 0.9 V turns on the regulator, and driving EN below 0.4 V puts the regulator into shutdown mode, reducing operating current to 120 nA nominal. |
| 5 | NC | unconnected | No connection; this pin can be tied to ground to improve thermal dissipation. |
| 6 | IN | power_in | Input pin; a small capacitor is needed from this pin to ground to assure stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | -0.3 | 6 | V | 5 | ||
| Enable voltage range | VEN | -0.3 | 6 | V | VIN or 6.0 V, whichever is less | 5 | |
| Output voltage range | VOUT | -0.3 | 6 | V | 5 | ||
| Operating junction temperature | TJ | -55 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| Input voltage | VIN | 2 | 5.5 | V | 5 | ||
| Output current | IOUT | 0 | 250 | mA | 5 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | 5 | ||
| Input voltage range | VIN | 2 | 5.5 | V | 6 | ||
| Output voltage range | VO | 0.9 | 5 | V | 6 | ||
| DC output accuracy | VOUT | -2 | 1 | 2 | % | VOUT + 0.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 200 mA | 6 |
| DC output accuracy | VOUT | -1 | 1 | % | VOUT + 0.3 V ≤ VIN ≤ 5.5 V, 0 mA ≤ IOUT ≤ 250 mA | 6 | |
| Load transient | ΔVOUT | -50 | 50 | mV | 1 mA to 200 mA or 200 mA to 1 mA in 1 μs, COUT = 1 μF | 6 | |
| Load transient | ΔVOUT | -65 | 65 | mV | 1 mA to 250 mA or 250 mA to 1 mA in 1 μs, COUT = 1 μF | 6 | |
| Dropout voltage | VDO | 130 | 200 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 200 mA | 6 | |
| Output current limit | ICL | 300 | 400 | 550 | mA | VOUT = 0.9 × VOUT(NOM) | 6 |
| Ground pin current | IGND | 7.9 | 12 | µA | IOUT = 0 mA, TJ = -40°C to +125°C | 6 | |
| Shutdown current (IGND) | ISHDN | 0.55 | 2 | µA | EN ≤ 0.4 V, 2.0 V < VIN ≤ 4.5 V, TJ = -40°C to +85°C | 6 | |
| Enable pin high (enabled) | VHI | 0.9 | V | 6 | |||
| Enable pin low (disabled) | VLO | 0 | 0.4 | V | 6 | ||
| Enable pin current | IEN | 40 | 500 | nA | EN = 5.5 V | 6 | |
| Undervoltage lock-out | UVLO | 1.85 | 1.9 | 1.95 | V | VIN rising | 6 |
| Power-supply rejection ratio | PSRR | 85 | dB | f = 10 Hz | 6 | ||
| Power-supply rejection ratio | PSRR | 75 | dB | f = 100 Hz | 6 | ||
| Power-supply rejection ratio | PSRR | 70 | dB | VIN = 2.3 V, f = 1 kHz | 6 | ||
| Power-supply rejection ratio | PSRR | 55 | dB | f = 10 kHz | 6 | ||
| Power-supply rejection ratio | PSRR | 40 | dB | f = 100 kHz | 6 | ||
| Power-supply rejection ratio | PSRR | 45 | dB | f = 1 MHz | 6 | ||
| Thermal shutdown temperature | TSD | 160 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown temperature | TSD | 140 | °C | Reset, temperature decreasing | 6 | ||
| Line regulation | ΔVO/ΔVIN | 8 | µV/V | VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA | 6 | ||
| Load regulation | ΔVO/ΔIOUT | 20 | µV/mA | 0 mA ≤ IOUT ≤ 250 mA | 6 | ||
| Dropout voltage | VDO | 6.5 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 10 mA | 6 | ||
| Dropout voltage | VDO | 32.5 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 50 mA | 6 | ||
| Dropout voltage | VDO | 65 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 100 mA | 6 | ||
| Dropout voltage | VDO | 162.5 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 250 mA | 6 | ||
| Ground pin current | IGND | 110 | µA | IOUT = 200 mA | 6 | ||
| Ground pin current | IGND | 130 | µA | IOUT = 250 mA | 6 | ||
| Shutdown current (IGND) | ISHDN | 0.12 | µA | VEN ≤ 0.4 V, VIN = 2 V, TJ = +25°C | 6 | ||
| Output voltage noise | VN | 33.5 | µVRMS | BW = 100 Hz to 100 kHz, VIN = 2.1 V, VOUT = 1.8 V, IOUT = 10 mA | 6 | ||
| Startup time | tSTR | 100 | µs | COUT = 1.0 μF, 0 ≤ IOUT ≤ 250 mA | 6 | ||
| Junction-to-ambient thermal resistance (DSE WSON) | RθJA | 190.5 | °C/W | DSE (WSON) 6 pins | 5 | ||
| Junction-to-case (top) thermal resistance (DSE WSON) | RθJC(top) | 94.9 | °C/W | DSE (WSON) 6 pins | 5 | ||
| Junction-to-board thermal resistance (DSE WSON) | RθJB | 149.3 | °C/W | DSE (WSON) 6 pins | 5 | ||
| Junction-to-top characterization parameter (DSE WSON) | ψJT | 6.4 | °C/W | DSE (WSON) 6 pins | 5 | ||
| Junction-to-board characterization parameter (DSE WSON) | ψJB | 152.8 | °C/W | DSE (WSON) 6 pins | 5 |
CAD (KiCad official)
- Symbol:
TPS72730DSET - Footprint:
Package_SON:WSON-6_1.5x1.5mm_P0.5mm - 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files:
tps72730dset-etched.step/tps72730dset-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps72730dset.step/tps72730dset.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
eb07c4ca05ae7371, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).