# TPS72325QDBVRQ1

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS72325QDBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin of the regulator. |
| 2 | IN | power_in | Input supply pin; the datasheet specifies VIN from -2.7V to -10V with an absolute maximum of -11V. |
| 3 | EN | input | Bipolar enable pin that turns the regulator on above +1.5V or below -1.5V and off between -0.4V and +0.4V, with a weak internal pulldown that lets it float to enable. |
| 4 | NR | passive | Noise-reduction pin for the fixed-voltage version; a capacitor to GND (10nF recommended for low noise) bypasses the internal bandgap noise. |
| 5 | OUT | power_out | Regulator output that requires a 2.2µF or larger ceramic capacitor with ESR between 0 and 0.5Ω for stability, placed as close to the pin as possible. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | -10 |  | -2.7 | V |  | 4 |
| Enable voltage range | VEN | -10 |  | 5 | V |  | 4 |
| Output current | IOUT | 0 |  | 200 | mA |  | 4 |
| Input capacitor (old chip) | CIN | 0.1 |  | 2.2 | µF |  | 4 |
| Output capacitor | COUT | 2.2 |  | 100 | µF |  | 4 |
| Operating junction temperature (recommended) | TJ | -40 |  | 125 | °C |  | 4 |
| IN input supply voltage | VIN | -11 |  | 0.3 | V |  | 4 |
| EN enable voltage | VEN |  |  | 5.5 | V | minimum printed as -VIN | 4 |
| OUT output voltage | VOUT | -11 |  | 0.3 | V |  | 4 |
| NR voltage range (old chip) | NR | -11 |  | 5.5 | V |  | 4 |
| NR voltage range (new chip) | NR | -6 |  | 0.3 | V |  | 4 |
| Operating junction temperature (absolute maximum) | TJ | -65 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance (new chip) | RθJA |  | 153.7 |  | °C/W |  | 5 |
| Junction-to-ambient thermal resistance (old chip) | RθJA |  | 180 |  | °C/W | 5-pin SOT-23 (DBV), old chip | 1 |
| Junction-to-case thermal resistance (top) | RθJC(top) |  | 73.4 |  | °C/W |  | 5 |
| Junction-to-board thermal resistance | RθJB |  | 34.8 |  | °C/W |  | 5 |
| Junction-to-top characterization parameter | ΨJT |  | 7.6 |  | °C/W |  | 5 |
| Junction-to-board characterization parameter | ΨJB |  | 34.5 |  | °C/W |  | 5 |
| Output voltage accuracy (old chip, TJ = 25°C) | VO | -1 |  | 1 | % | TJ = 25°C | 5 |
| Output voltage accuracy (old chip) | VO | -2 | 1 | 2 | % | -10V ≤ VI ≤ VO, 0.5V，10μA ≤ IO ≤ 200mA | 5 |
| Output voltage accuracy (new chip) | VO | -1.6 | 0.04 | 1.6 | % | -10V ≤ VI ≤ VO, 0.5V，10μA ≤ IO ≤ 200mA | 5 |
| Dropout voltage (old chip) | VDO |  | 280 | 500 | mV | IO = 200mA，VO = 0.96 × VO(NOM) | 5 |
| Dropout voltage (new chip) | VDO |  | 140 | 245 | mV |  | 5 |
| Input UVLO rising (new chip) | VUVLO+ | -2.4 |  | -2.1 | V |  | 5 |
| Input UVLO falling (new chip) | VUVLO- | -1.9 |  | -1.4 | V |  | 5 |
| Output current limit (old chip) | ILIM | 300 | 550 | 800 | mA | VO = 0.85 × VO(NOM) | 6 |
| Output current limit (new chip) | ILIM | 300 | 385 | 485 | mA | VO = 0.85 × VO(NOM) | 6 |
| Ground pin current (old chip, IO = 0 mA) | IGND |  | 130 | 200 | µA | IO = 0mA (IQ)，-10V ≤ VI ≤ VO, 0.5V | 6 |
| Ground pin current (old chip, IO = 200 mA) | IGND |  | 350 | 500 | µA | IO = 200mA，-10V ≤ VI ≤ VO, 0.5V | 6 |
| Ground pin current (new chip, IO = 0 mA) | IGND |  | 30 | 55 | µA | IO = 0mA (IQ)，-10V ≤ VI ≤ VO, 0.5V | 6 |
| Ground pin current (new chip, IO = 200 mA) | IGND |  | 290 | 450 | µA | IO = 200mA，-10V ≤ VI ≤ VO, 0.5V | 6 |
| Shutdown ground pin current (old chip) | ISHDN |  | 0.1 | 2 | µA | -0.4V ≤ VEN ≤ 0.4V，-10V ≤ VI ≤ VO, 0.5V | 6 |
| Shutdown ground pin current (new chip) | ISHDN |  | 0.7 | 2 | µA | -0.4V ≤ VEN ≤ 0.4V，-10V ≤ VI ≤ VO, 0.5V | 6 |
| EN pin current (old chip) | IEN |  | 0.1 | 2 |  | -10V ≤ VI ≤ VO, 0.5V，-10V ≤ VEN ≤ ±3.5V | 6 |
| EN pin current (new chip) | IEN |  | 0.6 | 2 |  |  | 6 |

## CAD (KiCad official)

- Symbol: `TPS72325QDBVRQ1`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps72325qdbvrq1-etched.step` / `tps72325qdbvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps72325qdbvrq1.step` / `tps72325qdbvrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps723-q1) (44 pp, sha256 `8ac5df49a742887a`, retrieved 2026-11-05, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps72325qdbvrq1-datasheet.pdf)