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page.json	tps72033qdrvrq1: specified limits as data (metadata.characteristics, 34 rows from the datasheet) · Ray	17d ago
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tps72033qdrvrq1-etched.glb	tps72033qdrvrq1: factory component page (tier=lcsc) · Ray	24d ago
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TPS72033QDRVRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS72033QDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT	output	Output pin; a 2.2-µF ceramic capacitor must be connected from this pin to ground for stability and to provide load transients.
2	NC	unconnected	No connection.
3	EN	input	Enable pin; a logic high signal turns the device on and regulates the voltage from IN to OUT, and a logic low turns the device off. Enable voltage is rated 0 V to 5.5 V under recommended operating conditions.
4	BIAS	input	Bias supply pin; TI recommends bypassing it with a ceramic capacitor to ground for better transient performance (CBIAS 0.1 µF nominal in recommended conditions), and VBIAS must be 2.6 V or VOUT + 1.4 V, whichever applies, up to 5.5 V.
5	GND	power_in	Ground pin.
6	IN	input	Input pin; maximum 4.5 V and VIN must not exceed VBIAS under all conditions, and it should be bypassed to ground with a ceramic capacitor.
7	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WSON-6-EP(2x2)
Category	Power Management (PMIC)
Pins	7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VIN input voltage (steady-state)	VIN	1.1			V		5
VBIAS bias voltage	VBIAS	2.6		5.5	V		5
Output voltage	VOUT	0.9		3.6	V		5
Output accuracy		-2		2	%	Over VBIAS, VIN, IOUT, TJ = –40°C to +125°C; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, VOUT + 0.5 V ≤ VIN ≤ 4.5 V, 0 mA ≤ IOUT ≤ 350 mA	5
Output accuracy (VIN floating)		-1		1	%	VIN floating; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, 0 μA ≤ IOUT ≤ 500 μA	5
VIN line transient		-200		200	μV	ΔVIN = 400 mV, tRISE = tFALL = 1 μs	5
VBIAS line transient		-0.8		0.8	mV	ΔVBIAS = 600 mV, tRISE = tFALL = 1 μs	5
Load transient		-15		15	mV	0 mA ≤ IOUT ≤ 350 mA, tRISE = tFALL = 1 μs	5
VIN dropout voltage	VDO_IN		110	200	mV	VIN = VOUT(NOM) – 0.1 V, (VBIAS – VOUT(NOM)) = 1.4 V, IOUT = 350 mA	5
VBIAS dropout voltage	VDO_BIAS		1.09	1.4	V	VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA	5
Output current limit	ICL	420	600	800	mA	VOUT = 0.9 × VOUT(NOM)	5
Ground pin current	IGND		54	80	μA	IOUT = 0 mA to 350 mA	5
Shutdown current (IGND)	ISHDN		0.5	2.5	μA	VEN ≤ 0.4 V	5
Enable pin low (disabled)	VEN(LO)	0		0.4	V		5
Undervoltage lockout		2.35	2.45	2.59	V	VBIAS rising	6
Operating junction temperature	TJ	-40		125	°C		6
Input voltage (steady-state) absolute maximum	VIN	-0.3			V		3
Peak transient input voltage	VIN_PEAK			5.5	V	Footnote (4): ≤1 ms each, ≤1000 occurrences over device lifetime	3
Bias voltage absolute maximum	VBIAS	-0.3		6	V		3
Enable voltage absolute maximum	VEN	-0.3		6	V		3
Output voltage absolute maximum	VOUT	-0.3		5	V		3
Operating junction temperature absolute maximum	TJ	-55		125	°C		3
Storage temperature	Tstg	-55		150	°C		3
Input voltage (steady-state) recommended	VIN	1.1			V		4
Bias voltage recommended	VBIAS			5.5	V		4
Output voltage recommended	VOUT	0.9		3.6	V		4
Peak output current	IOUT	0		350	mA		4
Enable voltage recommended	VEN	0		5.5	V		4
Junction-to-ambient thermal resistance	RθJA		66.5		°C/W		4
Junction-to-case (top) thermal resistance	RθJC(top)		86.2		°C/W		4
Junction-to-board thermal resistance	RθJB		36.1		°C/W		4
Junction-to-top characterization parameter	ψJT		1.7		°C/W		4
Junction-to-board characterization parameter	ψJB		36.6		°C/W		4
Junction-to-case (bottom) thermal resistance	RθJC(bot)		7.4		°C/W		4

CAD (KiCad official)

Symbol: TPS72033QDRVRQ1
Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
3D model files: tps72033qdrvrq1-etched.step / tps72033qdrvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps72033qdrvrq1.step / tps72033qdrvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (26 pp, sha256 1f171499f63bd1ce, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF