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TPS72018QDRVRQ1
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS72018QDRVRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
TPS72018QDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulated output pin; a 2.2-µF ceramic capacitor from this pin to ground is required for stability and load transients. |
| 2 | NC | unconnected | No connection. |
| 3 | EN | input | Enable pin; a logic high turns the device on and regulates IN to OUT, and a logic low turns the device off. |
| 4 | BIAS | input | Bias supply pin; TI recommends bypassing it with a ceramic capacitor to ground for better transient performance. |
| 5 | GND | power_in | Ground pin. |
| 6 | IN | input | Input pin, which can be a maximum of 4.5 V and must not exceed VBIAS; bypass it with a ceramic capacitor to ground. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (steady-state) | VIN | -0.3 | 5 | V | Max printed as VBIAS or 5 V (whichever is less) | 3 | |
| Peak transient input | VIN_PEAK | 5.5 | V | Note 4: ≤1 ms each, ≤1000 occurrences over device lifetime | 3 | ||
| Bias voltage | VBIAS | -0.3 | 6 | V | 3 | ||
| Enable voltage | VEN | -0.3 | 6 | V | 3 | ||
| Output voltage | VOUT | -0.3 | 5 | V | 3 | ||
| Operating junction temperature | TJ | -55 | 125 | °C | 3 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 3 | ||
| Input voltage (steady-state) | VIN | 1.1 | 4.5 | V | Max printed as VBIAS or 4.5 V (whichever is less) | 4 | |
| Bias voltage | VBIAS | 2.6 | 5.5 | V | Min printed as 2.6 or VOUT + 1.4 (footnote 2) | 4 | |
| Output voltage | VOUT | 0.9 | 3.6 | V | 4 | ||
| Peak output current | IOUT | 0 | 350 | mA | 4 | ||
| Enable voltage | VEN | 0 | 5.5 | V | 4 | ||
| Output capacitance maximum ESR | 250 | mΩ | Footnote 3 on COUT: maximum ESR must be less than 250 mΩ | 4 | |||
| Input voltage (steady-state) | VIN | 1.1 | 4.5 | V | Max printed as VBIAS or 4.5 V (whichever is less) | 5 | |
| Bias voltage | VBIAS | 2.6 | 5.5 | V | 5 | ||
| Output voltage | VOUT | 0.9 | 3.6 | V | 5 | ||
| Output accuracy | -2 | 2 | % | TJ = -40°C to +125°C; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V; VOUT + 0.5 V ≤ VIN ≤ 4.5 V; 0 mA ≤ IOUT ≤ 350 mA | 5 | ||
| Output accuracy, VIN floating | -1 | 1 | % | VIN floating; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V; 0 μA ≤ IOUT ≤ 500 μA | 5 | ||
| VIN line transient | -200 | 200 | μV | ΔVIN = 400 mV, tRISE = tFALL = 1 μs | 5 | ||
| VBIAS line transient | -0.8 | 0.8 | mV | ΔVBIAS = 600 mV, tRISE = tFALL = 1 μs | 5 | ||
| Load transient | -15 | 15 | mV | 0 mA ≤ IOUT ≤ 350 mA, tRISE = tFALL = 1 μs | 5 | ||
| VIN dropout voltage | VDO_IN | 110 | 200 | mV | VIN = VOUT(NOM) – 0.1 V, (VBIAS – VOUT(NOM)) = 1.4 V, IOUT = 350 mA | 5 | |
| VBIAS dropout voltage | VDO_BIAS | 1.09 | 1.4 | V | VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA | 5 | |
| Output current limit | ICL | 420 | 600 | 800 | mA | VOUT = 0.9 × VOUT(NOM) | 5 |
| Ground pin current | IGND | 54 | 80 | μA | IOUT = 0 mA to 350 mA | 5 | |
| Shutdown current (IGND) | ISHDN | 0.5 | 2.5 | μA | VEN ≤ 0.4 V | 5 | |
| Enable pin low (disabled) | VEN(LO) | 0 | 0.4 | V | 5 | ||
| Undervoltage lockout | UVLO | 2.35 | 2.45 | 2.59 | V | VBIAS rising | 6 |
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 66.5 | °C/W | DRV (WSON) package | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 86.2 | °C/W | DRV (WSON) package | 4 | ||
| Junction-to-board thermal resistance | RθJB | 36.1 | °C/W | DRV (WSON) package | 4 | ||
| Junction-to-top characterization parameter | ψJT | 1.7 | °C/W | DRV (WSON) package | 4 | ||
| Junction-to-board characterization parameter | ψJB | 36.6 | °C/W | DRV (WSON) package | 4 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 7.4 | °C/W | DRV (WSON) package | 4 |
CAD (KiCad official)
- Symbol:
TPS72018QDRVRQ1 - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
tps72018qdrvrq1-etched.step/tps72018qdrvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps72018qdrvrq1.step/tps72018qdrvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
1f171499f63bd1ce, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).