component

TPS72018DRVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps72018drvrfactory-2.0.0extractor-text

Verified TPS72018DRVR

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 7 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS72018DRVR · WSON-6-EP(2x2) · 7 pins
  • ✓copper: 7 copper pads, none touching another net
  • ✓datasheet: all 7 pin names found in the 39-page datasheet
  • ✓distributor: lcsc C2870363, digikey 296-50149-2-ND, mouser 595-TPS72018DRVR
  • ✓family: WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1pzfyw49/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 7 pins = 7 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 7 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps72018drvr.kicad_sym✓ tps72018drvr.kicad_mod✓ tps72018drvr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers tps72018drvr: viewers · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
tps72018drvr-etched.glb Publish 0.1.0 · Ray 2h ago
tps72018drvr-etched.step tps72018drvr: factory component page (tier=mfr) · Ray 2h ago
tps72018drvr-hero.glb tps72018drvr: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
tps72018drvr-hero.overlay.json Publish 0.1.0 · Ray 2h ago
tps72018drvr.glb Publish 0.1.0 · Ray 2h ago
tps72018drvr.kicad_mod Publish 0.1.0 · Ray 2h ago
tps72018drvr.kicad_sym Publish 0.1.0 · Ray 2h ago
tps72018drvr.lbr Publish 0.1.0 · Ray 2h ago
tps72018drvr.step Publish 0.1.0 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 7 pins · Ray 2h ago

TPS72018DRVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS72018DRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground, for stability and to provide load transients.
2 NC unconnected No connection.
3 EN input Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A logic low on this pin turns off the device.
4 BIAS input Bias supply pin. TI recommends bypassing this input with a ceramic capacitor to ground for better transient performance.
5 GND power_in Ground pin.
6 IN input Input pin. This pin can be a maximum of 4.5 V; VIN must not exceed VBIAS. Bypass this input with a ceramic capacitor to ground.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage VOUT 0.9 3.6 V 4
Input voltage (steady-state) VIN 1.1 V Maximum printed as VBIAS or 4.5 V 4
Bias voltage VBIAS 2.5 5.5 V Minimum printed as 2.5 or VOUT + 1.4 (footnote 2) 4
Peak output current IOUT 0 350 mA 4
Input voltage (steady-state) VIN -0.3 V Maximum printed as VBIAS or 5 3
Peak transient input voltage VIN_PEAK 5.5 V Footnote 4: for durations no longer than 1 ms each, for a total of no more than 1000 occurrences over the lifetime of the device 3
Bias voltage VBIAS -0.3 6 V 3
Enable voltage VEN -0.3 6 V 3
Output voltage VOUT -0.3 5 V 3
Operating junction temperature TJ -55 125 °C 3
Storage temperature Tstg -55 150 °C 3
Output voltage accuracy (nominal) VOUT -3 3 mV Nominal TJ = 25°C 5
Output voltage accuracy (over conditions) VOUT -2 2 % Over VBIAS, VIN, IOUT, TJ = -40°C to 125°C; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, VOUT + 0.5 V ≤ VIN ≤ 4.5 V, 0 mA ≤ IOUT ≤ 350 mA 5
Output voltage accuracy (VIN floating) VOUT -1 1 % VIN floating, VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, 0 μA ≤ IOUT ≤ 500 μA 5
VIN dropout voltage VDO_IN 110 200 mV VIN = VOUT(NOM), 0.1 V, (VBIAS, VOUT(NOM)) = 1.4 V, IOUT = 350 mA 5
VBIAS dropout voltage VDO_BIAS 1.09 1.4 V VIN = VOUT(NOM) + 0.3 V, IOUT = 350 mA 5
Output current limit ICL 420 525 800 mA VOUT = 0.9 × VOUT(NOM) 5
Ground pin current IGND 54 80 μA IOUT = 0 mA to 350 mA 5
Shutdown current (IGND) ISHDN 0.5 2 μA VEN ≤ 0.4 V, TJ = -40°C to 85°C 5
Enable pin low (disabled) VEN(LO) 0 0.4 V 5
Undervoltage lockout UVLO 2.41 2.45 2.49 V VBIAS rising 5
Operating junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 66.5 °C/W DRV (SON) 6-pin 4
Junction-to-case (top) thermal resistance RθJC(top) 86.2 °C/W DRV (SON) 6-pin 4
Junction-to-board thermal resistance RθJB 36.1 °C/W DRV (SON) 6-pin 4
Junction-to-top characterization parameter ψJT 1.7 °C/W DRV (SON) 6-pin 4
Junction-to-board characterization parameter ψJB 36.6 °C/W DRV (SON) 6-pin 4
Junction-to-case (bottom) thermal resistance RθJC(bot) 7.4 °C/W DRV (SON) 6-pin 4

CAD (KiCad official)

  • Symbol: TPS72018DRVR
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps72018drvr-etched.step / tps72018drvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps72018drvr.step / tps72018drvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 aa52c96cf07d505f, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF