# TPS72009QDRVRQ1

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS72009QDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Output pin; a 2.2-µF ceramic capacitor connected from this pin to ground is required for stability and load transients. |
| 2 | NC | unconnected | No connection. |
| 3 | EN | input | Enable pin; a logic high turns the device on and regulates the voltage from IN to OUT, and a logic low turns it off. |
| 4 | BIAS | input | Bias supply pin; TI recommends bypassing this input with a ceramic capacitor to ground for better transient performance. |
| 5 | GND | power_in | Ground pin. |
| 6 | IN | input | Input pin; it can be a maximum of 4.5 V, VIN must not exceed VBIAS, and it should be bypassed with a ceramic capacitor to ground. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | 1.1 |  |  | V |  | 5 |
| Bias voltage | VBIAS | 2.6 |  | 5.5 | V |  | 5 |
| Output voltage | VOUT | 0.9 |  | 3.6 | V |  | 5 |
| Output accuracy |  | -2 |  | 2 | % | Over VBIAS, VIN, IOUT, TJ = -40°C to +125°C; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, VOUT + 0.5 V ≤ VIN ≤ 4.5 V, 0 mA ≤ IOUT ≤ 350 mA | 5 |
| Output accuracy (VOUT < 1.2 V) |  | -25 |  | 25 | mV | Over VBIAS, VIN, IOUT, TJ = -40°C to +125°C; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, VOUT + 0.5 V ≤ VIN ≤ 4.5 V, 0 mA ≤ IOUT ≤ 350 mA, VOUT < 1.2 V | 5 |
| Output accuracy (VIN floating) |  | -1 |  | 1 | % | VIN floating; VOUT + 1.4 V ≤ VBIAS ≤ 5.5 V, 0 μA ≤ IOUT ≤ 500 μA | 5 |
| VIN line transient |  | -200 |  | 200 | μV | ΔVIN = 400 mV, tRISE = tFALL = 1 μs | 5 |
| VBIAS line transient |  | -0.8 |  | 0.8 | mV | ΔVBIAS = 600 mV, tRISE = tFALL = 1 μs | 5 |
| Load transient |  | -15 |  | 15 | mV | 0 mA ≤ IOUT ≤ 350 mA, tRISE = tFALL = 1 μs | 5 |
| Output current limit | ICL | 420 | 600 | 800 | mA | VOUT = 0.9 × VOUT(NOM) | 5 |
| Ground pin current | IGND |  | 54 | 80 | μA | IOUT = 0 mA to 350 mA | 5 |
| Shutdown current (IGND) | ISHDN |  | 0.5 | 2.5 | μA | VEN ≤ 0.4 V | 5 |
| Enable pin high (enabled) | VEN(HI) | 1.1 |  |  | V |  | 5 |
| Enable pin low (disabled) | VEN(LO) | 0 |  | 0.4 | V |  | 5 |
| Undervoltage lockout |  | 2.35 | 2.45 | 2.59 | V | VBIAS rising | 6 |
| Operating junction temperature (electrical characteristics) | TJ | -40 |  | 125 | °C |  | 6 |
| Input voltage (steady-state, absolute max) | VIN | -0.3 |  |  | V | Maximum is VBIAS or 5 V, whichever is less | 3 |
| Peak transient input voltage | VIN_PEAK |  |  | 5.5 | V | Each transient ≤1 ms, ≤1000 occurrences over device lifetime | 3 |
| Bias voltage (absolute max) | VBIAS | -0.3 |  | 6 | V |  | 3 |
| Enable voltage (absolute max) | VEN | -0.3 |  | 6 | V |  | 3 |
| Output voltage (absolute max) | VOUT | -0.3 |  | 5 | V |  | 3 |
| Operating junction temperature (absolute max) | TJ | -55 |  | 125 | °C |  | 3 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 3 |
| Input voltage (steady-state, recommended) | VIN | 1.1 |  |  | V | Maximum is VBIAS or 4.5 V (footnote 1) | 4 |
| Bias voltage (recommended) | VBIAS |  |  | 5.5 | V | Minimum is 2.6 V or VOUT + 1.4 V, whichever is greater (footnote 2) | 4 |
| Output voltage (recommended) | VOUT | 0.9 |  | 3.6 | V |  | 4 |
| Peak output current (recommended) | IOUT | 0 |  | 350 | mA |  | 4 |
| Enable voltage (recommended) | VEN | 0 |  | 5.5 | V |  | 4 |
| Input capacitance | CIN | 1 |  |  | µF |  | 4 |
| Bias capacitance | CBIAS | 0.1 |  |  | µF |  | 4 |
| Output capacitance | COUT | 2.2 |  |  | µF | Maximum ESR must be less than 250 mΩ | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 66.5 |  | °C/W | DRV (WSON) 6-pin, JEDEC board | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 86.2 |  | °C/W | DRV (WSON) 6-pin | 4 |
| Junction-to-board thermal resistance | RθJB |  | 36.1 |  | °C/W | DRV (WSON) 6-pin | 4 |
| Junction-to-top characterization parameter | ψJT |  | 1.7 |  | °C/W | DRV (WSON) 6-pin | 4 |
| Junction-to-board characterization parameter | ψJB |  | 36.6 |  | °C/W | DRV (WSON) 6-pin | 4 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 7.4 |  | °C/W | DRV (WSON) 6-pin | 4 |

## CAD (KiCad official)

- Symbol: `TPS72009QDRVRQ1`
- Footprint: `Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm`
- 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `tps72009qdrvrq1-etched.step` / `tps72009qdrvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps72009qdrvrq1.step` / `tps72009qdrvrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps720-q1) (26 pp, sha256 `1f171499f63bd1ce`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps72009qdrvrq1-datasheet.pdf)