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TPS71728QDRVRQ1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS71728QDRVRQ1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS71728QDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out This pin is the regulated output voltage, and a minimum capacitance of 1 µF is required for stability from this pin to ground.
2 NR passive Fixed-voltage versions only: an external capacitor on this pin bypasses noise from the internal band gap to lower output noise.
3 GND power_in Ground pin; ground return connections to the input and output capacitors and to this pin should be made as close to the GND pin as possible.
4 EN input Driving EN above VEN(high) turns on the regulator, driving it below VEN(low) puts the regulator into standby and disables the output, and VEN absolute maximum is VIN + 0.3 V or 7 V, whichever is greater.
5 N/C unconnected Not connected; this pin can be tied to ground to improve thermal dissipation.
6 IN power_in Input to the device, with a 0.1 µF to 1 µF capacitor recommended for better performance; the input supply operates from 2.5 V to 6.5 V and VIN absolute maximum is 7 V.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 7 V 5
Noise reduction pin voltage VNR -0.3 3.6 V 5
Enable pin voltage VEN -0.3 V Maximum printed as VIN + 0.3 V (or 7 V, whichever is greater) 5
Output voltage VOUT -0.3 7 V 5
Ambient temperature TA -40 125 °C 5
Operating junction temperature TJ -55 150 °C 5
Storage temperature Tstg -55 150 °C 5
Input voltage VIN 2.5 6.5 V 6
Output voltage VOUT 0.9 5 V 6
Output current IOUT 0 150 mA 6
Enable voltage VEN 0 V Maximum printed as VIN 6
Input capacitor CIN 1 µF 6
Noise reduction capacitor CNR 10 nF 6
Output capacitor COUT 1 100 µF 6
Junction temperature TJ -40 125 °C 6
Input voltage range VIN 2.5 6.5 V 7
Output voltage range (TPS717-Q1) VOUT 0.9 5 V 7
Output accuracy (VOUT ≥ 1 V), over VIN, IOUT, temperature VOUT -3 3 % VOUT + 0.5 V ≤ VIN ≤ 6.5 V, 0 mA ≤ IOUT ≤ 150 mA 7
Dropout voltage VDO 170 300 mV VIN = VOUT(nom) – 0.1 V, IOUT = 150 mA 7
Output current limit (fixed output) ILIM (fixed) 200 325 575 mA VOUT = 0.9 × VOUT(nom) 7
Ground pin current IGND 45 80 μA IOUT = 0.1 mA 7
Shutdown current (IGND) ISHDN 0.2 1.5 μA VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V, TA = –40°C to 125°C 7
Shutdown current (IGND) ISHDN 0.9 μA VEN ≤ 0.4 V, 4.5 V ≤ VIN ≤ 6.5 V, TA = –40°C to 125°C 7
Shutdown current (IGND), DRV package ISHDN 2 μA VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V, TA = –40°C to 125°C, DRV package 7
Enable high (enabled) VEN(high) 1.2 6.5 V VIN ≤ 5.5 V 7
Enable high (enabled) VEN(high) 1.25 6.5 V 5.5 V < VIN ≤ 6.5 V 7
Enable low (shutdown) VEN(low) 0 0.4 V 7
Enable pin current, enabled IEN(high) 0.02 1 μA EN = 6.5 V 7
Undervoltage lockout UVLO 2.45 2.49 V VIN rising 7
Thermal shutdown temperature Tsd 160 °C Shutdown, temperature increasing 7
Thermal shutdown reset temperature Tsd 140 °C Reset, temperature decreasing 7
UVLO hysteresis UVLO hysteresis 150 mV VIN falling 7
Thermal resistance, junction-to-ambient (DRV, WSON 6-pin) RθJA 71.1 °C/W DRV (WSON) 6-pin package 6
Thermal resistance, junction-to-case (top) (DRV, WSON 6-pin) RθJC(top) 96.5 °C/W DRV (WSON) 6-pin package 6
Thermal resistance, junction-to-board (DRV, WSON 6-pin) RθJB 40.5 °C/W DRV (WSON) 6-pin package 6
Junction-to-top characterization parameter (DRV, WSON 6-pin) ψJT 2.7 °C/W DRV (WSON) 6-pin package 6
Junction-to-board characterization parameter (DRV, WSON 6-pin) ψJB 40.9 °C/W DRV (WSON) 6-pin package 6
Thermal resistance, junction-to-case (bottom) (DRV, WSON 6-pin) RθJC(bot) 10.7 °C/W DRV (WSON) 6-pin package 6
Ground pin current IGND 100 μA IOUT = 150 mA 7
Line regulation ΔVOUT(ΔVIN) 125 μV/V VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V, IOUT = 5 mA 7
Load regulation ΔVOUT(ΔIOUT) 70 μV/mA 0 mA ≤ IOUT ≤ 150 mA 7
Power-supply rejection ratio PSRR 70 dB VIN = 3.8 V, VOUT = 2.8 V, IOUT = 150 mA, f = 100 Hz 7
Power-supply rejection ratio PSRR 67 dB VIN = 3.8 V, VOUT = 2.8 V, IOUT = 150 mA, f = 10 kHz 7
Power-supply rejection ratio PSRR 45 dB VIN = 3.8 V, VOUT = 2.8 V, IOUT = 150 mA, f = 1 MHz 7
Output noise voltage Vn 95 μVRMS/V BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 2.8 V, IOUT = 10 mA, CNR = none 7
Output noise voltage Vn 25 μVRMS/V BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 2.8 V, IOUT = 10 mA, CNR = 0.001 μF 7
Output noise voltage Vn 12.5 μVRMS/V BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 2.8 V, IOUT = 10 mA, CNR = 0.01 μF 7
Output noise voltage Vn 11.5 μVRMS/V BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 2.8 V, IOUT = 10 mA, CNR = 0.1 μF 7
Startup time tSTR 0.16 ms VOUT = 90% VOUT(nom), RL = 19 Ω, COUT = 1 μF, 1.6 V < VOUT < VOUT(max), CNR = 0.01 μF 7

CAD (KiCad official)

  • Symbol: TPS71728QDRVRQ1
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps71728qdrvrq1-etched.step / tps71728qdrvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps71728qdrvrq1.step / tps71728qdrvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 2be05880cde1a822, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF