# TPS71727DSER

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6(1.5x1.5)

TPS71727DSER from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | This pin is the regulated output voltage, and a minimum capacitance of 1 μF is required for stability from this pin to ground. |
| 2 | GND | power_in | Ground pin; ground return connections for the input and output capacitors and the LDO should be made as close to this pin as possible. |
| 3 | NR/FB | passive | On this fixed-voltage version the pin is the noise reduction (NR) capacitor connection, which filters internal band-gap noise to lower output noise; the feedback (FB) function applies only to the adjustable version. |
| 4 | EN | input | Driving EN above VEN(high) turns the regulator on and driving it below VEN(low) places it in standby; the pin must not be left floating, and its absolute maximum is VIN + 0.3 V or 7 V, whichever is greater. |
| 5 | N/C | unconnected | Not connected; this pin can be tied to ground to improve thermal dissipation. |
| 6 | IN | power_in | Input to the device, operating from 2.5 V to 6.5 V with a 7 V absolute maximum, and a 0.1-μF to 1-μF capacitor is recommended for better performance. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.5 |  | 6.5 | V |  | 5 |
| Output voltage range (TPS717xx fixed versions) | VOUT | 0.9 |  | 5 | V |  | 5 |
| Output accuracy, nominal |  | -2.5 |  | 2.5 | mV | Nominal TJ = 25°C | 5 |
| Output accuracy, VOUT < 1.0 V |  | -30 |  | 30 | mV | Over VIN, IOUT, temp; VOUT + 0.5 V ≤ VIN ≤ 6.5 V; 0 mA ≤ IOUT ≤ 150 mA | 5 |
| Output accuracy, VOUT ≥ 1.0 V |  | -3 |  | 3 | % | Over VIN, IOUT, temp; VOUT + 0.5 V ≤ VIN ≤ 6.5 V; 0 mA ≤ IOUT ≤ 150 mA | 5 |
| Dropout voltage | VDO |  | 170 | 300 | mV | IOUT = 150 mA (VIN = VOUT(nom) – 0.1 V) | 5 |
| Output current limit (fixed output) | ILIM | 200 | 325 | 575 | mA | VOUT = 0.9 × VOUT(nom) | 5 |
| Ground pin current | IGND |  | 45 | 80 | µA | IOUT = 0.1 mA | 5 |
| Shutdown current (IGND) | ISHDN |  | 0.2 | 1.5 | µA | VEN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V | 5 |
| Enable high (enabled), VIN ≤ 5.5 V | VEN(high) | 1.2 |  | 6.5 | V | VIN ≤ 5.5 V | 5 |
| Enable high (enabled), 5.5 V < VIN ≤ 6.5 V | VEN(high) | 1.25 |  | 6.5 | V | 5.5 V < VIN ≤ 6.5 V | 5 |
| Enable low (shutdown) | VEN(low) | 0 |  | 0.4 | V |  | 5 |
| Enable pin current, enabled | IEN(high) |  | 0.02 | 1 | µA | EN = 6.5 V | 5 |
| Undervoltage lockout | UVLO | 2.41 | 2.45 | 2.49 | V | VIN rising | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Input voltage | VIN | 2.5 |  | 6.5 | V |  | 4 |
| Output voltage | VOUT | 0.9 |  | 5 | V |  | 4 |
| Output current | IOUT | 0 |  | 150 | mA |  | 4 |
| Enable voltage | VEN | 0 |  |  | V | Maximum printed as VIN, not a number | 4 |
| Output capacitor | COUT | 1 |  | 100 | µF |  | 4 |
| Junction temperature (recommended) | TJ | -40 |  | 125 | °C |  | 4 |
| Input voltage (absolute maximum) | VIN | -0.3 |  | 7 | V | All voltages with respect to GND | 4 |
| Noise reduction pin voltage (absolute maximum) | VNR | -0.3 |  | 3.6 | V | All voltages with respect to GND | 4 |
| Enable voltage (absolute maximum) | VEN | -0.3 |  |  | V | Maximum printed as VIN + 0.3 V or 7 V, whichever is greater | 4 |
| Output voltage (absolute maximum) | VOUT | -0.3 |  | 7 | V | All voltages with respect to GND | 4 |
| Operating junction temperature (absolute maximum) | TJ | -55 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 4 |
| Junction-to-ambient thermal resistance (DSE, WSON-6 1.5 mm) | RθJA |  | 190.5 |  | °C/W |  | 4 |
| Junction-to-case (top) thermal resistance (DSE) | RθJC(top) |  | 94.9 |  | °C/W |  | 4 |
| Junction-to-board thermal resistance (DSE) | RθJB |  | 149.3 |  | °C/W |  | 4 |
| Junction-to-top characterization parameter (DSE) | ψJT |  | 6.4 |  | °C/W |  | 4 |
| Junction-to-board characterization parameter (DSE) | ψJB |  | 152.8 |  | °C/W |  | 4 |

## CAD (KiCad official)

- Symbol: `TPS71727DSER`
- Footprint: `Package_SON:WSON-6_1.5x1.5mm_P0.5mm`
- 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files: `tps71727dser-etched.step` / `tps71727dser-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps71727dser.step` / `tps71727dser.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps717) (45 pp, sha256 `9d6a9da698418596`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps71727dser-datasheet.pdf)