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TPS71530QDCKRM3Q1

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SC-70-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS71530QDCKRM3Q1

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SC-70-5

TPS71530QDCKRM3Q1 from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect pin that is not connected internally; connect to ground for best thermal performance or leave floating.
2 GND power_in Ground pin.
3 NC unconnected No connect pin that is not connected internally; connect to ground for best thermal performance or leave floating.
4 IN power_in Input supply pin, with the recommended input supply voltage range of 2.5 V to 24 V.
5 OUT power_out Regulator output; requires an effective output capacitance of at least 0.47 µF for stability.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage (IO = 10 mA) VIN 2.5 24 V IO = 10 mA 6
Input supply voltage (IO = 50 mA) VIN 3 24 V IO = 50 mA 6
Output voltage accuracy -4 4 % VOUT + 1 V ≤ VIN ≤ 24 V, 100 µA ≤ IOUT ≤ 50 mA 6
Ground pin current (new chip) IGND 3.2 4.1 µA 0 ≤ IOUT ≤ 50 mA, TJ = -40°C to 85°C 6
Ground pin current (new chip) IGND 3.2 4.3 µA 0 mA ≤ IOUT ≤ 50 mA 6
Ground pin current (new chip) IGND 4.5 µA 0 mA ≤ IOUT ≤ 50 mA, VIN = 24 V 6
Load regulation ΔVOUT (ΔIOUT) 22 mV IOUT = 100 μA to 50 mA 6
Output voltage line regulation (new chip) ΔVOUT (ΔVIN) 20 22 mV VOUT(NOM) + 1 V ≤ VIN ≤ 24 V 6
Output current limit (new chip) ICL 125 350 mA VOUT = 0 V, VIN ≥ 3.5 V 6
Output current limit (new chip) ICL 90 350 mA VOUT = 0 V, VIN < 3.5 V 6
Dropout voltage (new chip) VDO 415 525 mV IOUT = 50 mA, VIN = VOUT(nom), 0.1 V 6
Input voltage absolute maximum (new chip) VIN -0.3 30 V VIN (for new chip only) 4
Input capacitor CIN 0 0.047 µF Input capacitor 4
Output capacitor (new chip) COUT 1 µF Output capacitor (for new chip only); effective output capacitance of 0.47 µF minimum for stability 4
Operating junction temperature TJ -40 125 °C Operating junction temperature 4
Junction temperature TJ -40 150 °C Junction, TJ 4
Storage temperature Tstg -65 150 °C Storage, Tstg 4
Junction-to-ambient thermal resistance (new chip) RθJA 195.7 °C/W DCK (SC-70) 5 pins, new chip 5
Junction-to-case (top) thermal resistance (new chip) RθJC(top) 88.2 °C/W DCK (SC-70) 5 pins, new chip 5
Junction-to-board thermal resistance (new chip) RθJB 40.7 °C/W DCK (SC-70) 5 pins, new chip 5

CAD (KiCad official)

  • Symbol: TPS71530QDCKRM3Q1
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: tps71530qdckrm3q1-etched.step / tps71530qdckrm3q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps71530qdckrm3q1.step / tps71530qdckrm3q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 0c616251e0bf3453, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF