# TPS71401DCKT

**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SC-70-5

TPS71401DCKT from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback input for the adjustable output. Connect the mid-point of an external resistor divider from OUT to GND here to program VOUT from 1.205 V to 8.8 V. Internal reference is 1.2 V (typ); feedback bias current is ~2 nA. |
| 2 | GND | power_in | Device ground return. All voltages are referenced to this pin. |
| 3 | NC | unconnected | No connect. Not connected internally; tie to ground for best thermal performance or leave floating. |
| 4 | IN | power_in | Input supply pin, 2.5 V to 10 V operating range (30 V absolute max on the new chip). Bypass to GND with a 0.1 µF or larger capacitor (0.047 µF or larger for the legacy chip). |
| 5 | OUT | power_out | Regulated output, up to 80 mA. Requires a 1 µF or larger capacitor to GND for stability on the new chip (≥0.47 µF for the legacy chip). Dropout is ~415 mV at 50 mA / ~650 mV at 80 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SC-70-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Ordering variants

Same part, different packaging or reel option.

- `TPS71401DCKT`
- `TPS71401DCKTDCKR`
- `TPS71401DCKTDRVT`
- `TPS71401DCKTDRVR`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN (for legacy chip only) | VIN | -0.3 |  | 24 | V |  | 4 |
| VOUT (for legacy chip only) | VOUT | -0.3 |  | 9.9 | V |  | 4 |
| VFB (for adjustable output legacy chip only) | VFB | -0.3 |  | 4.5 | V |  | 4 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Input voltage range | VIN | 2.5 |  | 10 | V | IO = 10 mA | 6 |
| Input voltage range | VIN | 3 |  | 10 | V | IO = 80mA | 6 |
| Output voltage range (TPS71401) | VOUT |  |  | 8.8 | V |  | 6 |
| Internal reference (legacy chip) (TPS71401) | VFB | 1.12 | 1.2 | 1.24 | V |  | 6 |
| Load regulation | ΔVOUT (ΔIOUT) |  |  | 30 | mV | IOUT = 1 mA to 80 mA | 6 |
| Output voltage line regulation | ΔVOUT (ΔVIN) |  |  | 5 | mV | VOUT + 1 V < VIN ≤ 10 V | 6 |
| Feedback pin bias current | IFB BIAS |  |  | 2 | nA | IOUT = 0 mA, VIN = 3V to 10V, VOUT = 1.2V | 6 |
| Output noise voltage (legacy chip) | Vn |  |  | 575 | μVrms | BW = 200 Hz to 100 kHz, COUT = 10 μF, IOUT = 50 mA | 6 |
| Ground pin current (legacy chip) | IGND |  | 3.2 | 4.2 | μA | 1 mA ≤ IOUT ≤ 80mA, TJ = –40°C to 85°C | 6 |
| Ground pin current (legacy chip) | IGND |  | 3.2 | 5.8 | μA | 1 mA ≤ IOUT ≤ 80mA | 6 |
| Ground pin current (legacy chip) | IGND |  |  | 7.4 | μA | 1 mA ≤ IOUT ≤ 80mA, VIN = 10 V | 6 |
| Output current limit (legacy chip) | ICL | 100 |  | 1100 | mA | VOUT = 0 V | 6 |
| Dropout voltage (legacy chip) | VDO |  | 670 | 1300 | mV | VIN = VOUT(nom) – 0.1 V, IOUT = 80 mA | 6 |
| Input supply voltage | VIN | 2.5 |  | 10 | V |  | 4 |
| Output voltage | VOUT | 1.205 |  | 8.8 | V |  | 4 |
| Output current | IOUT | 0 |  | 80 | mA |  | 4 |
| Input capacitor | CIN | 0 |  | 0.047 | µF |  | 4 |
| Output capacitor (for legacy chip only) | COUT | 0.47 |  | 1 | µF |  | 4 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 253.8 |  | °C/W | DCK (SC-70) 5-pin, legacy chip column | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 73.7 |  | °C/W | DCK (SC-70) 5-pin, legacy chip column | 5 |
| Junction-to-board thermal resistance | RθJB |  | 84.6 |  | °C/W | DCK (SC-70) 5-pin, legacy chip column | 5 |
| Junction-to-top characterization parameter | ψJT |  | 1.1 |  | °C/W | DCK (SC-70) 5-pin, legacy chip column | 5 |
| Junction-to-board characterization parameter | ψJB |  | 83.9 |  | °C/W | DCK (SC-70) 5-pin, legacy chip column | 5 |

## CAD (KiCad official)

- Symbol: `TPS71401DCKT`
- Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5`
- 3D model: SC-70-5 (KiCad packages3D, STEP)
- 3D model files: `tps71401dckt-etched.step` / `tps71401dckt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps71401dckt.step` / `tps71401dckt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps714) (None pp, sha256 `3794ea8f66f454a2`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps71401dckt-datasheet.pdf)