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TPS7101QDR

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS7101QDR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

TPS7101QDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the regulator; the datasheet states that all voltage values are with respect to network terminal ground.
2 EN input Enable input where a TTL high signal (VIH minimum 2 V) shuts down the regulator and a low level (VIL maximum 0.5 V) enables it.
3 IN power_in Unregulated input supply; the recommended input voltage for the TPS7101Q is 2.5 V to 10 V, and the absolute maximum input range is -0.3 V to 11 V.
4 IN power_in Unregulated input supply, tied in parallel with pin 3; the recommended input voltage for the TPS7101Q is 2.5 V to 10 V, and the absolute maximum input range is -0.3 V to 11 V.
5 OUT power_out Regulator output; the recommended output current range is 0 mA to 500 mA, with an absolute maximum output current of 2 A, and it requires an output capacitor for stability.
6 OUT power_out Regulator output, tied in parallel with pin 5; the recommended output current range is 0 mA to 500 mA, with an absolute maximum output current of 2 A.
7 SENSE/FB input Feedback input for the adjustable TPS7101, where the output is set by an external divider against a 1.178 V typical reference, giving a 1.2 V to 9.75 V programmable range.
8 PG output Open-drain power-good output that goes low when the output drops to between 92% and 98% of nominal and requires a pullup resistor; its input/output rating follows the -0.3 V to 11 V absolute maximum range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range (TPS7101Q) VI 2.5 10 V TPS7101Q, minimum is absolute lower limit for TPS7101 5
High-level input voltage at EN VIH 2 V 5
Low-level input voltage at EN VIL 0.5 V 5
Output current range IO 0 500 mA 5
Operating virtual junction temperature range TJ -40 125 °C 5
Input voltage range VI, PG, SENSE, EN -0.3 11 V with respect to network terminal ground 4
Output current IO 2 A 4
Operating virtual junction temperature range TJ -55 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 4
Junction-to-ambient thermal resistance (D package) RθJA 172 °C/W D package 5
Junction-to-case thermal resistance (D package) RθJC 57 °C/W D package 5
Ground current (active mode) IQ 285 350 µA 25°C, EN ≤ 0.5 V, VI = VO + 1 V 6
Ground current (active mode) IQ 460 µA -40°C to 125°C, EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mA, VI ≥ VO + 1 V 6
Input current (standby mode) II 0.5 µA 25°C, EN = VI, 2.7 V ≤ VI ≤ 10 V 6
Input current (standby mode) II 2 µA -40°C to 125°C, EN = VI, 2.7 V ≤ VI ≤ 10 V 6
Output current limit IO 1.2 2 A 25°C, VO = 0, VI = 10 V 6
Output current limit IO 2 A -40°C to 125°C, VO = 0, VI = 10 V 6
Pass-element leakage current in standby mode 0.5 µA 25°C, EN = VI, 2.7 V ≤ VI ≤ 10 V 6
Pass-element leakage current in standby mode 1 µA -40°C to 125°C, EN = VI, 2.7 V ≤ VI ≤ 10 V 6
PG leakage current 0.02 0.5 µA 25°C, normal operation, VPG = 10 V 6
PG leakage current 0.5 µA -40°C to 125°C, normal operation, VPG = 10 V 6
Output voltage temperature coefficient 61 75 ppm/°C -40°C to 125°C 6
Thermal shutdown junction temperature 165 °C 6
EN logic high (standby mode) 2 V -40°C to 125°C, 2.5 V ≤ VI ≤ 6 V 6
EN logic high (standby mode) 2.7 V -40°C to 125°C, 6 V ≤ VI ≤ 10 V 6
EN logic low (active mode) 0.5 V 25°C, 2.7 V ≤ VI ≤ 10 V 6
EN hysteresis voltage 50 mV 25°C 6
EN input current -0.5 0.5 µA 25°C, 0 V ≤ VI ≤ 10 V 6
Minimum VI for active pass element 2.05 2.5 V 25°C 6
Minimum VI for active pass element 2.5 V -40°C to 125°C 6
Minimum VI for valid PG 1.06 1.5 V 25°C, IPG = 300 µA 6
Minimum VI for valid PG 1.9 V -40°C to 125°C, IPG = 300 µA 6
Reference voltage (measured at FB with OUT connected to FB) Vref 1.178 V 25°C, VI = 3.5 V, IO = 10 mA 7
Reference voltage (measured at FB with OUT connected to FB) Vref 1.143 1.213 V -40°C to 125°C, 2.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA 7
Reference voltage temperature coefficient 61 75 ppm/°C -40°C to 125°C 7
Pass-element series resistance rDS(on) 0.7 1 Ω 25°C, VI = 2.4 V, 50 µA ≤ IO ≤ 150 mA 7
Pass-element series resistance rDS(on) 1 Ω -40°C to 125°C, VI = 2.4 V, 50 µA ≤ IO ≤ 150 mA 7
Pass-element series resistance rDS(on) 0.83 1.3 Ω 25°C, VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 7
Pass-element series resistance rDS(on) 1.3 Ω -40°C to 125°C, VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 7
Pass-element series resistance rDS(on) 0.52 0.85 Ω 25°C, VI = 2.9 V, 50 µA ≤ IO ≤ 500 mA 7
Pass-element series resistance rDS(on) 0.85 Ω -40°C to 125°C, VI = 2.9 V, 50 µA ≤ IO ≤ 500 mA 7
Pass-element series resistance rDS(on) 0.32 Ω 25°C, VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 7
Pass-element series resistance rDS(on) 0.23 Ω 25°C, VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 7
Input regulation 18 mV 25°C, VI = 2.5 V to 10 V, 50 µA ≤ IO ≤ 500 mA 7
Input regulation 25 mV -40°C to 125°C, VI = 2.5 V to 10 V, 50 µA ≤ IO ≤ 500 mA 7
Output regulation 14 mV 25°C, IO = 5 mA to 500 mA, 2.5 V ≤ VI ≤ 10 V 7
Output regulation 25 mV -40°C to 125°C, IO = 5 mA to 500 mA, 2.5 V ≤ VI ≤ 10 V 7
Output regulation 22 mV 25°C, IO = 50 µA to 500 mA, 2.5 V ≤ VI ≤ 10 V 7
Output regulation 54 mV -40°C to 125°C, IO = 50 µA to 500 mA, 2.5 V ≤ VI ≤ 10 V 7
Ripple rejection f = 120 Hz 48 59 dB 25°C, IO = 50 µA 7
Ripple rejection f = 120 Hz 44 dB -40°C to 125°C, IO = 50 µA 7
Ripple rejection f = 120 Hz 45 54 dB 25°C, IO = 500 mA 7
Output noise-spectral density 2 µV/√Hz 25°C, f = 120 Hz 7
Output noise voltage 95 µVrms 25°C, 10 Hz ≤ f ≤ 100 kHz, CO = 4.7 µF, CSR = 1 Ω 7
Output noise voltage 89 µVrms 25°C, 10 Hz ≤ f ≤ 100 kHz, CO = 10 µF, CSR = 1 Ω 7
Output noise voltage 74 µVrms 25°C, 10 Hz ≤ f ≤ 100 kHz, CO = 100 µF, CSR = 1 Ω 7
PG trip-threshold voltage VPG 1.101 1.145 V -40°C to 125°C, VFB voltage decreasing from above VPG 7
PG hysteresis voltage 12 mV 25°C, measured at VFB 7
PG output low voltage 0.1 0.4 V 25°C, IPG = 400 µA, VI = 2.13 V 7
PG output low voltage 0.4 V -40°C to 125°C, IPG = 400 µA, VI = 2.13 V 7
FB input current -10 0.1 10 nA 25°C 7
FB input current -20 20 nA -40°C to 125°C 7

CAD (KiCad official)

  • Symbol: TPS7101QDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps7101qdr-etched.step / tps7101qdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps7101qdr.step / tps7101qdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 6da6cbc880c8f130, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF