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TPS709A33DBVT

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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps709a33dbvtfactory-2.0.0extractor-text

Verified TPS709A33DBVT

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 5 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS709A33DBVT · SOT-23-5 · 5 pins
  • ✓copper: 5 copper pads, none touching another net
  • ✓datasheet: all 5 pin names found in the 43-page datasheet
  • ✓distributor: lcsc C2870359, digikey 296-43266-2-ND, mouser 595-TPS709A33DBVT
  • ✓family: SOT-23-5
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6s_y570l/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 5 pins = 5 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 5 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps709a33dbvt.kicad_sym✓ tps709a33dbvt.kicad_mod✓ tps709a33dbvt.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

TPS709A33DBVT

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TPS709A33DBVT from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Regulated output voltage; connect a 2.2-µF or greater ceramic capacitor from this pin to ground to assure stability.
2 GND power_in Ground pin, which is electrically connected to the thermal pad; connect the thermal pad to the GND plane for improved thermal performance.
3 IN input Unregulated input to the device, with a recommended input voltage range of 2.7 V to 30 V.
4 NC unconnected No internal connection.
5 EN input Enable pin: drive high to enable the device and low to enter low current shutdown; it can be left floating to enable the device, and the maximum voltage must remain below 6.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 2.7 30 V 5
Output voltage range VOUT 1.2 6.5 V 5
DC output accuracy VOUT -1 1 % VOUT >= 3.3 V 5
Line regulation ΔVOUT 3 10 mV (VOUT(nom) + 1 V, 2.7 V) <= VIN <= 30 V 5
Load regulation ΔVOUT 20 50 mV VIN = VOUT(typ) + 1.5 V or 3 V (whichever is greater), 100 µA <= IOUT <= 150 mA 5
Dropout voltage TPS70933 at 50 mA VDO 295 650 mV TPS70933, IOUT = 50 mA 5
Dropout voltage TPS70933 at 150 mA VDO 960 1400 mV TPS70933, IOUT = 150 mA 5
Output current limit I(CL) 200 320 500 mA VOUT = 0.9 × VOUT(nom) 5
Ground pin current IGND 1.3 2.05 µA IOUT = 0 mA, VOUT <= 3.3 V 5
Shutdown current ISHUTDOWN 150 nA VEN <= 0.4 V, VIN = 2.7 V 5
Start-up time tSTR 200 600 µs VOUT(nom) <= 3.3 V 5
Enable pin low-level input voltage VEN(LOW) 0 0.4 V Device disabled 5
EN pin current IEN 300 nA EN = 1.0 V, VIN = 5.5 V 5
Input voltage range (recommended) VIN 2.7 30 V 4
Output voltage (recommended) VOUT 1.2 6.5 V 4
Enable voltage (recommended) VEN 0 6.5 V 4
Operating junction temperature (recommended) TJ -40 125 °C 4
Input voltage (absolute maximum) VIN -0.3 32 V all voltages with respect to GND 4
Enable voltage (absolute maximum) VEN -0.3 7 V all voltages with respect to GND 4
Output voltage (absolute maximum) VOUT -0.3 7 V all voltages with respect to GND 4
Operating junction temperature (absolute maximum) TJ -55 150 °C 4
Storage temperature Tstg -55 150 °C 4
Junction-to-ambient thermal resistance (DBV) RθJA 212.1 °C/W DBV 5-pin package 4
Junction-to-case (top) thermal resistance (DBV) RθJC(top) 78.5 °C/W DBV 5-pin package 4
Junction-to-board thermal resistance (DBV) RθJB 39.5 °C/W DBV 5-pin package 4
Junction-to-top characterization parameter (DBV) ψJT 2.86 °C/W DBV 5-pin package 4
Junction-to-board characterization parameter (DBV) ψJB 38.7 °C/W DBV 5-pin package 4

CAD (KiCad official)

  • Symbol: TPS709A33DBVT
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps709a33dbvt-etched.step / tps709a33dbvt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps709a33dbvt.step / tps709a33dbvt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (43 pp, sha256 8c14e3efae738a27, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF