component
TPS70918DRVR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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tps70918drvr: specified limits as data (metadata.characteristics, 23 rows from the datasheet)
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TPS70918DRVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
TPS70918DRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage; connect a small 2.2-µF or greater ceramic capacitor from this pin to ground to assure stability. |
| 2 | NC | unconnected | No internal connection. |
| 3 | GND | power_in | Ground reference for the device; the thermal pad is electrically connected to this GND node. |
| 4 | EN | input | Enable pin: drive high to enable the device and low to put it into low-current shutdown; it may be left floating to enable the device, and the maximum voltage must remain below 6.5 V. |
| 5 | NC | unconnected | No internal connection. |
| 6 | IN | power_in | Unregulated input to the device, which accepts 2.7 V to 30 V per the Recommended Operating Conditions. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | 30 | V | 5 | ||
| Output voltage range | VOUT | 1.2 | 6.5 | V | 5 | ||
| VOUT DC output accuracy | VOUT | -2 | 2 | % | VOUT < 3.3 V | 5 | |
| Line regulation | ΔVOUT | 3 | 10 | mV | (VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 30 V | 5 | |
| Load regulation | 20 | 50 | mV | VIN = VOUT(typ) + 1.5 V or 3 V (whichever is greater), 100 µA ≤ IOUT ≤ 150 mA | 5 | ||
| Output current limit | I(CL) | 200 | 320 | 500 | mA | VOUT = 0.9 × VOUT(nom) | 5 |
| Ground pin current | IGND | 1.3 | 2.05 | µA | IOUT = 0 mA, VOUT ≤ 3.3 V | 5 | |
| Start-up time | tSTR | 200 | 600 | µs | VOUT(nom) ≤ 3.3 V | 5 | |
| Input voltage | VIN | -0.3 | 32 | V | all voltages with respect to GND | 4 | |
| Enable voltage | VEN | -0.3 | 7 | V | all voltages with respect to GND | 4 | |
| Output voltage | VOUT | -0.3 | 7 | V | all voltages with respect to GND | 4 | |
| Operating junction temperature | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage | VIN | 2.7 | 30 | V | 4 | ||
| Output voltage | VOUT | 1.2 | 6.5 | V | 4 | ||
| Enable voltage | VEN | 0 | 6.5 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance (DRV, 6 pins) | RθJA | 73.1 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (DRV, 6 pins) | RθJC(top) | 97 | °C/W | 4 | |||
| Junction-to-board thermal resistance (DRV, 6 pins) | RθJB | 42.6 | °C/W | 4 | |||
| Junction-to-top characterization parameter (DRV, 6 pins) | ψJT | 2.9 | °C/W | 4 | |||
| Junction-to-board characterization parameter (DRV, 6 pins) | ψJB | 42.9 | °C/W | 4 | |||
| Junction-to-case (bottom) thermal resistance (DRV, 6 pins) | RθJC(bot) | 12.8 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TPS70918DRVR - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
tps70918drvr-etched.step/tps70918drvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps70918drvr.step/tps70918drvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (44 pp, sha256
18967ac390121fa9, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS70918DRVR
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
TPS70918DRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage; connect a small 2.2-µF or greater ceramic capacitor from this pin to ground to assure stability. |
| 2 | NC | unconnected | No internal connection. |
| 3 | GND | power_in | Ground reference for the device; the thermal pad is electrically connected to this GND node. |
| 4 | EN | input | Enable pin: drive high to enable the device and low to put it into low-current shutdown; it may be left floating to enable the device, and the maximum voltage must remain below 6.5 V. |
| 5 | NC | unconnected | No internal connection. |
| 6 | IN | power_in | Unregulated input to the device, which accepts 2.7 V to 30 V per the Recommended Operating Conditions. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | | 30 | V | | 5 |
| Output voltage range | VOUT | 1.2 | | 6.5 | V | | 5 |
| VOUT DC output accuracy | VOUT | -2 | | 2 | % | VOUT < 3.3 V | 5 |
| Line regulation | ΔVOUT | | 3 | 10 | mV | (VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 30 V | 5 |
| Load regulation | | | 20 | 50 | mV | VIN = VOUT(typ) + 1.5 V or 3 V (whichever is greater), 100 µA ≤ IOUT ≤ 150 mA | 5 |
| Output current limit | I(CL) | 200 | 320 | 500 | mA | VOUT = 0.9 × VOUT(nom) | 5 |
| Ground pin current | IGND | | 1.3 | 2.05 | µA | IOUT = 0 mA, VOUT ≤ 3.3 V | 5 |
| Start-up time | tSTR | | 200 | 600 | µs | VOUT(nom) ≤ 3.3 V | 5 |
| Input voltage | VIN | -0.3 | | 32 | V | all voltages with respect to GND | 4 |
| Enable voltage | VEN | -0.3 | | 7 | V | all voltages with respect to GND | 4 |
| Output voltage | VOUT | -0.3 | | 7 | V | all voltages with respect to GND | 4 |
| Operating junction temperature | TJ | -55 | | 150 | °C | | 4 |
| Storage temperature | Tstg | -55 | | 150 | °C | | 4 |
| Input voltage | VIN | 2.7 | | 30 | V | | 4 |
| Output voltage | VOUT | 1.2 | | 6.5 | V | | 4 |
| Enable voltage | VEN | 0 | | 6.5 | V | | 4 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 4 |
| Junction-to-ambient thermal resistance (DRV, 6 pins) | RθJA | | 73.1 | | °C/W | | 4 |
| Junction-to-case (top) thermal resistance (DRV, 6 pins) | RθJC(top) | | 97 | | °C/W | | 4 |
| Junction-to-board thermal resistance (DRV, 6 pins) | RθJB | | 42.6 | | °C/W | | 4 |
| Junction-to-top characterization parameter (DRV, 6 pins) | ψJT | | 2.9 | | °C/W | | 4 |
| Junction-to-board characterization parameter (DRV, 6 pins) | ψJB | | 42.9 | | °C/W | | 4 |
| Junction-to-case (bottom) thermal resistance (DRV, 6 pins) | RθJC(bot) | | 12.8 | | °C/W | | 4 |
## CAD (KiCad official)
- Symbol: `TPS70918DRVR`
- Footprint: `Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm`
- 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `tps70918drvr-etched.step` / `tps70918drvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps70918drvr.step` / `tps70918drvr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps709) (44 pp, sha256 `18967ac390121fa9`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps70918drvr-datasheet.pdf)