Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TPS70851PWP

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20

TPS70851PWP from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 VIN1 power_in Input voltage of regulator 1; internal bias voltages are powered from VIN1.
3 VIN1 power_in Input voltage of regulator 1; internal bias voltages are powered from VIN1.
4 MR input Manual reset input, active low, pulled up internally with a 6-µA pull-up current to VIN1.
5 EN1 input Active-low enable for VOUT1; applying a high signal shuts down regulator 1.
6 EN2 input Active-low enable for VOUT2; applying a high signal shuts down regulator 2.
7 RESET output Open-drain, active-low SVS (power-on reset) output that requires an external pull-up resistor and can be left floating if unused.
8 GND power_in Ground.
9 VIN2 power_in Input voltage of regulator 2.
10 VIN2 power_in Input voltage of regulator 2.
11 NC unconnected No connection.
12 VOUT2 power_out Output voltage of regulator 2 (125 mA maximum on regulator 2).
13 VOUT2 power_out Output voltage of regulator 2 (125 mA maximum on regulator 2).
14 VSENSE2/FB2 input Regulator 2 output voltage sense for fixed-voltage versions, or feedback input for the adjustable version; must be connected to the external feedback divider or as short as possible to VOUT2.
15 PG2 output Open-drain power-good output, low when VOUT2 is below 95% of its nominal regulated voltage, requires a pull-up resistor.
16 PG1 output Open-drain power-good output, low when VOUT1 is below 95% of its nominal regulated voltage, requires a pull-up resistor.
17 VSENSE1/FB1 input Regulator 1 output voltage sense for fixed-voltage versions, or feedback input for the adjustable version; must be connected to the external feedback divider or as short as possible to VOUT1.
18 VOUT1 power_out Output voltage of regulator 1 (250 mA maximum on regulator 1).
19 VOUT1 power_out Output voltage of regulator 1 (250 mA maximum on regulator 1).
20 NC unconnected No connection.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage, VOUT1 3.3 V output VO 3.234 3.366 V 4.3 V < VIN < 6 V 5
Output voltage, VOUT2 1.8 V output VO 1.764 1.836 V 2.8 V < VIN < 6 V 5
Quiescent current (GND current), regulator 1 and regulator 2 190 230 µA EN1 = EN2 = 0 V 5
Output voltage line regulation ∆VO/VO 0.1 %/V VO + 1 V < VIN ≤ 6 V 5
Output current limit, regulator 1 1.6 1.9 A VOUT = 0 V 5
Output current limit, regulator 2 0.75 1 A VOUT = 0 V 5
UVLO threshold 2.4 2.65 V 5
RESET pulse duration t(RESET) 80 120 160 ms 5
RESET minimum input voltage for valid RESET 1 1.3 V I(RESET) = 300 µA, V(RESET) ≤ 0.8 V 5
RESET output low voltage 0.15 0.4 V VIN = 3.5 V, I(RESET) = 1 mA 5
PGx minimum input voltage for valid PGx 1 1.3 V I(PGx) = 300 µA, V(PGx) ≤ 0.8 V 6
PGx trip threshold voltage 92 95 98 %VOUT VO decreasing 6
PGx output low voltage 0.15 0.4 V VIN = 2.7 V, I(PGx) = 1 mA 6
Input current (ENx) -1 1 µA 6
Dropout voltage, VOUT1 140 mV IO = 250 mA, VIN1 = 3.2 V 6
Input voltage range, VIN1 and VIN2 (absolute maximum) VIN1, VIN2 -0.3 7 V 3
Voltage range at EN1, EN2 (absolute maximum) -0.3 7 V 3
Output voltage range, VOUT1 and VSENSE1 (absolute maximum) 5.5 V 3
Output voltage range, VOUT2 and VSENSE2 (absolute maximum) 5.5 V 3
Maximum RESET, PG1, PG2 voltage 7 V 3
Operating virtual junction temperature range (absolute maximum) TJ -40 150 °C 3
Storage temperature range Tstg -65 150 °C 3
Input voltage, VI (regulator 1 and 2) VI 2.7 6 V 4
Output current, IO (regulator 1) IO 0 500 mA 4
Output current, IO (regulator 2) IO 0 250 mA 4
Operating virtual junction temperature TJ -40 125 °C 4
Continuous total power dissipation, PWP, 0 CFM 3.067 W TA ≤ +25°C 4
Continuous total power dissipation, PWP, 0 CFM 1.687 W TA = +70°C 4
Continuous total power dissipation, PWP, 0 CFM 1.227 W TA = +85°C 4
Thermal resistance junction-to-ambient, 20-terminal PWP RθJA 32.6 °C/W no airflow 29

CAD (KiCad official)

  • Symbol: TPS70851PWP
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps70851pwp-etched.step / tps70851pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps70851pwp.step / tps70851pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 1606e377c0b89405, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF