component
TPS70702PWPR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS70702PWPR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP
TPS70702PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection; the datasheet lists this pin as not connected internally. |
| 2 | VIN1 | power_in | Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps the regulators off until VIN1 reaches 2.5 V. |
| 3 | VIN1 | power_in | Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps the regulators off until VIN1 reaches 2.5 V. |
| 4 | MR1 | input | Manual reset input 1, active low, with an internal 6-µA pull-up to VIN1; pulling it low triggers a POR (RESET). |
| 5 | MR2 | input | Manual reset input 2, active low, with an internal 6-µA pull-up to VIN1; pulling it low triggers a POR (RESET). |
| 6 | EN | input | Active-low enable; a high level puts both regulators in sleep mode (input current about 1 µA at TJ = +25°C) and a low level enables the device. |
| 7 | SEQ | input | Power-up sequence control: high or open makes VOUT2 power up first, low makes VOUT1 power up first; the pin has an internal 6-µA pull-up to VIN1. |
| 8 | GND | power_in | Ground connection for the device. |
| 9 | VIN2 | power_in | Input voltage of regulator 2. |
| 10 | VIN2 | power_in | Input voltage of regulator 2. |
| 11 | NC | unconnected | No connection; the datasheet lists this pin as not connected internally. |
| 12 | VOUT2 | power_out | Output voltage of regulator 2, which can supply up to 125 mA. |
| 13 | VOUT2 | power_out | Output voltage of regulator 2, which can supply up to 125 mA. |
| 14 | VSENSE2/FB2 | input | Regulator 2 output sense for fixed-voltage versions (connect as close as possible to VOUT2) or feedback input for the adjustable version, which must connect to the external feedback divider. |
| 15 | RESET | output | Open-drain active-low power-on reset output that indicates VOUT2 and MR1/MR2 status; it goes high-impedance 120 ms after VOUT2 exceeds 95% of its regulated voltage and requires a pull-up resistor. |
| 16 | PG1 | output | Open-drain power-good output for regulator 1 that goes high-impedance when VOUT1 reaches 95% of its regulated voltage and low when it falls below that level; it requires a pull-up resistor. |
| 17 | VSENSE1/FB1 | input | Regulator 1 output sense for fixed-voltage versions (connect as close as possible to VOUT1) or feedback input for the adjustable version, which must connect to the external feedback divider. |
| 18 | VOUT1 | power_out | Output voltage of regulator 1, which can supply up to 250 mA. |
| 19 | VOUT1 | power_out | Output voltage of regulator 1, which can supply up to 250 mA. |
| 20 | NC | unconnected | No connection; the datasheet lists this pin as not connected internally. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS70702PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps70702pwpr-etched.step/tps70702pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps70702pwpr.step/tps70702pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (45 pp, sha256
47c201c539729fd2, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS70702PWPR
**Texas Instruments** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-20-EP
TPS70702PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection; the datasheet lists this pin as not connected internally. |
| 2 | VIN1 | power_in | Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps the regulators off until VIN1 reaches 2.5 V. |
| 3 | VIN1 | power_in | Input voltage of regulator 1; internal bias voltages are powered from VIN1, and the UVLO circuit keeps the regulators off until VIN1 reaches 2.5 V. |
| 4 | MR1 | input | Manual reset input 1, active low, with an internal 6-µA pull-up to VIN1; pulling it low triggers a POR (RESET). |
| 5 | MR2 | input | Manual reset input 2, active low, with an internal 6-µA pull-up to VIN1; pulling it low triggers a POR (RESET). |
| 6 | EN | input | Active-low enable; a high level puts both regulators in sleep mode (input current about 1 µA at TJ = +25°C) and a low level enables the device. |
| 7 | SEQ | input | Power-up sequence control: high or open makes VOUT2 power up first, low makes VOUT1 power up first; the pin has an internal 6-µA pull-up to VIN1. |
| 8 | GND | power_in | Ground connection for the device. |
| 9 | VIN2 | power_in | Input voltage of regulator 2. |
| 10 | VIN2 | power_in | Input voltage of regulator 2. |
| 11 | NC | unconnected | No connection; the datasheet lists this pin as not connected internally. |
| 12 | VOUT2 | power_out | Output voltage of regulator 2, which can supply up to 125 mA. |
| 13 | VOUT2 | power_out | Output voltage of regulator 2, which can supply up to 125 mA. |
| 14 | VSENSE2/FB2 | input | Regulator 2 output sense for fixed-voltage versions (connect as close as possible to VOUT2) or feedback input for the adjustable version, which must connect to the external feedback divider. |
| 15 | RESET | output | Open-drain active-low power-on reset output that indicates VOUT2 and MR1/MR2 status; it goes high-impedance 120 ms after VOUT2 exceeds 95% of its regulated voltage and requires a pull-up resistor. |
| 16 | PG1 | output | Open-drain power-good output for regulator 1 that goes high-impedance when VOUT1 reaches 95% of its regulated voltage and low when it falls below that level; it requires a pull-up resistor. |
| 17 | VSENSE1/FB1 | input | Regulator 1 output sense for fixed-voltage versions (connect as close as possible to VOUT1) or feedback input for the adjustable version, which must connect to the external feedback divider. |
| 18 | VOUT1 | power_out | Output voltage of regulator 1, which can supply up to 250 mA. |
| 19 | VOUT1 | power_out | Output voltage of regulator 1, which can supply up to 250 mA. |
| 20 | NC | unconnected | No connection; the datasheet lists this pin as not connected internally. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
## CAD (KiCad official)
- Symbol: `TPS70702PWPR`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps70702pwpr-etched.step` / `tps70702pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps70702pwpr.step` / `tps70702pwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps707) (45 pp, sha256 `47c201c539729fd2`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps70702pwpr-datasheet.pdf)