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TPS70625DRVR

Public Made by Adom

by adom

Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs Publish 0.1.0 · Ray 19d ago
viewers tps70625drvr: viewers · Ray 19d ago
package.json Publish 0.1.0 · Ray 19d ago
page.json tps70625drvr: specified limits as data (metadata.characteristics, 26 rows from the datasheet) · Ray 17d ago
README.md tps70625drvr: specified limits as data (metadata.characteristics, 26 rows from the datasheet) · Ray 17d ago
tps70625drvr-etched.glb tps70625drvr: factory component page (tier=lcsc) · Ray 19d ago
tps70625drvr-etched.step tps70625drvr: factory component page (tier=lcsc) · Ray 19d ago
tps70625drvr-hero.glb tps70625drvr: hero GLB from the etched model (keeps the MPN mark) · Ray 19d ago
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tps70625drvr.glb Publish 0.1.0 · Ray 19d ago
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tps70625drvr.step Publish 0.1.0 · Ray 19d ago

TPS70625DRVR

Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)

TPS70625DRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage; connect a small 2.2-µF or greater ceramic capacitor from this pin to ground to assure stability, with COUT specified at 2 µF to 47 µF.
2 NC unconnected No internal connection.
3 GND power_in Ground reference for the device.
4 EN input Enable pin: driving high enables the device and driving low puts it into low-current shutdown; it may be left floating to enable the device, and the maximum voltage must remain below 6.5 V.
5 NC unconnected No internal connection.
6 IN power_in Unregulated input to the device, with recommended VIN of 2.7 V to 6.5 V and absolute maximum of 7 V.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range (VIN) VIN 2.7 6.5 V 4
Output voltage (VOUT) VOUT 1.2 5 V 4
Output current (IOUT) IOUT 0 150 mA 4
Enable voltage (VEN) VEN 0 6.5 V 4
Input capacitor (CIN) CIN 0 1 µF 4
Output capacitor (COUT) COUT 2 2.2 47 µF 4
Operating junction temperature (TJ) TJ -40 125 °C 4
Input voltage (VIN) VIN -0.3 7 V 4
Enable voltage (VEN) VEN -0.3 7 V 4
Output voltage (VOUT) VOUT -0.3 7 V 4
Junction temperature (TJ) TJ -55 150 °C 4
Storage temperature (Tstg) Tstg -55 150 °C 4
DC output accuracy VOUT(accuracy) -2 2 % VOUT < 3.3 V 5
Line regulation 3 10 mV (VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 6.5 V 5
Load regulation ΔVOUT 20 50 mV VIN = VOUT(nom) + 1.5 V or 3 V (whichever is greater), 100 µA ≤ IOUT ≤ 150 mA 5
Output current limit I(CL) 200 320 500 mA VOUT = 0.9 × VOUT(nom) 5
Ground pin current IGND 1.3 2.55 µA IOUT = 0 mA, VOUT ≤ 3.3 V 5
Enable pin high (enabled) VEN(HI) 0.9 V Enable pin high (enabled) 5
Enable pin high (disabled) VEN(HI) 0 0.4 V Enable pin high (disabled) 5
Start-up time (tSTR) tSTR 200 600 µs VOUT(nom) ≤ 3.3 V 5
Junction-to-ambient thermal resistance (RθJA) RθJA 73.1 °C/W DRV package, 6 pins 4
Junction-to-case (top) thermal resistance (RθJC(top)) RθJC(top) 97 °C/W DRV package, 6 pins 4
Junction-to-board thermal resistance (RθJB) RθJB 42.6 °C/W DRV package, 6 pins 4
Junction-to-top characterization parameter (ψJT) ψJT 2.9 °C/W DRV package, 6 pins 4
Junction-to-board characterization parameter (ψJB) ψJB 42.9 °C/W DRV package, 6 pins 4
Junction-to-case (bottom) thermal resistance (RθJC(bot)) RθJC(bot) 12.8 °C/W DRV package, 6 pins 4

CAD (KiCad official)

  • Symbol: TPS70625DRVR
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps70625drvr-etched.step / tps70625drvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps70625drvr.step / tps70625drvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 cca0ee52828baf76, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF