component
TPS70612DBVR
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS70612DBVR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
TPS70612DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Unregulated input to the device, specified from 2.7 V to 6.5 V in the Recommended Operating Conditions. |
| 2 | GND | power_in | Ground pin, electrically connected to the thermal pad, which should be connected to the GND plane for improved thermal performance. |
| 3 | EN | input | Driving this pin high enables the device and driving it low puts the device into low current shutdown; the maximum voltage must remain below 6.5 V. |
| 4 | NC | unconnected | No internal connection. |
| 5 | OUT | power_out | Regulated output voltage; connect a small 2.2-µF or greater ceramic capacitor from this pin to ground to assure stability. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VIN | -0.3 | 7 | V | all voltages with respect to GND | 4 | |
| Enable voltage | VEN | -0.3 | 7 | V | all voltages with respect to GND | 4 | |
| Output voltage | VOUT | -0.3 | 7 | V | all voltages with respect to GND | 4 | |
| Junction temperature | TJ | -55 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage | VIN | 2.7 | 6.5 | V | 4 | ||
| Output voltage | VOUT | 1.2 | 5 | V | 4 | ||
| Output current | IOUT | 0 | 150 | mA | 4 | ||
| Enable voltage | VEN | 0 | 6.5 | V | 4 | ||
| Input capacitor | CIN | 0 | 1 | µF | 4 | ||
| Output capacitor | COUT | 2 | 2.2 | 47 | µF | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Input voltage range | VIN | 2.7 | 6.5 | V | 5 | ||
| Output voltage range | VOUT | 1.2 | 5 | V | 5 | ||
| DC output accuracy | VOUT(accuracy) | -2 | 2 | % | VOUT < 3.3 V | 5 | |
| Line regulation | 3 | 10 | mV | (VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 6.5 V | 5 | ||
| Load regulation | ΔVOUT | 20 | 50 | mV | VIN = VOUT(nom) + 1.5 V or 3 V (whichever is greater), 100 µA ≤ IOUT ≤ 150 mA | 5 | |
| Output current limit | I(CL) | 200 | 320 | 500 | mA | VOUT = 0.9 × VOUT(nom) | 5 |
| Ground pin current | IGND | 1.3 | 2.55 | µA | IOUT = 0 mA, VOUT ≤ 3.3 V | 5 | |
| Shutdown current | ISHDN | 150 | nA | VEN ≤ 0.4 V, VIN = 2.7 V | 5 | ||
| Power-supply rejection ratio | PSRR | 80 | dB | f = 10 Hz | 5 | ||
| Power-supply rejection ratio | PSRR | 62 | dB | f = 100 Hz | 5 | ||
| Power-supply rejection ratio | PSRR | 52 | dB | f = 1 kHz | 5 | ||
| Output noise voltage | Vn | 190 | µVRMS | BW = 10 Hz to 100 kHz, IOUT = 10 mA, VIN = 2.7 V, VOUT = 1.2 V | 5 | ||
| Enable pin high (enabled) | VEN(HI) | 0.9 | V | Enable pin high (enabled) | 5 | ||
| Enable pin high (disabled) | VEN(HI) | 0 | 0.4 | V | Enable pin high (disabled) | 5 | |
| EN pin current | IEN | 300 | nA | EN = 1.0 V, VIN = 5.5 V | 5 | ||
| Reverse current (flowing out of IN pin) | IREV | 10 | nA | VOUT = 3 V, VIN = VEN = 0 V | 5 | ||
| Reverse current (flowing into OUT pin) | IREV | 100 | nA | VOUT = 3 V, VIN = VEN = 0 V | 5 | ||
| Thermal shutdown temperature | TSD | 158 | °C | Shutdown, temperature increasing | 5 | ||
| Thermal shutdown reset temperature | TSD | 140 | °C | Reset, temperature decreasing | 5 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Start-up time | tSTR | 200 | 600 | µs | VOUT(nom) ≤ 3.3 V | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 212.1 | °C/W | DBV (5 pins) | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 78.5 | °C/W | DBV (5 pins) | 4 | ||
| Junction-to-board thermal resistance | RθJB | 39.5 | °C/W | DBV (5 pins) | 4 | ||
| Junction-to-top characterization parameter | ψJT | 2.86 | °C/W | DBV (5 pins) | 4 | ||
| Junction-to-board characterization parameter | ψJB | 38.7 | °C/W | DBV (5 pins) | 4 |
CAD (KiCad official)
- Symbol:
TPS70612DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps70612dbvr-etched.step/tps70612dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps70612dbvr.step/tps70612dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
9c11e3964e376b3e, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).